PORTLAND, Ore. -- Integrating III-V transistors into 22-nm design flows may soon be possible, according to the Massachusetts Institute of Technology (MIT) researches who demonstrated indium-gallium arsenide (InGaAs) transistors at the International Electron Devices Meeting (IEDM) this week in San Francisco.
Since 2009, Intel has been tweaking high-k metal gate stacks for III-V transistor channels while Toyohashi University of Technology claimed last year to have solved the lattice mismatch in depositing gallium arsenide on silicon substrates.
MIT demonstrated an indium gallium arsenide transistor that it claims can be shrunk to smaller dimensions than silicon. Built by MIT’s Microsystems Technology Laboratories, the researchers claim their 22-nm demonstration transistor show that InGaAs is a promising candidate to replace silicon at advanced technology nodes.
Employing the same MOSFET architecture as conventional CMOS transistors, the researchers used self-aligning techniques to fabricate the nanoscale gate. Using molecular beam epitaxy to deposit the channel, molybdenum was then deposited using e-beam lithography to form the source and drain electrodes. The middle gate was then etched with oxide deposited on top after which evaporated molybdenum was fired at the surface.
"With a combination of etching and deposition we can get the gate nestled [between the source and drain electrodes] with tiny gaps around it," MIT said.
The MIT is next aiming to improve the electrical performance of their InGaAs transistor by optimizing the stack to reduce resistance. The team's ultimate goal is to produce III-V transistors that are faster than silicon and have gate lengths as short as 10 nm.
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