LONDON – STMicroelectronics has announced that its 28-nm fully depleted silicon-on-insulator (FDSOI) is available for pre-production from its Crolles 300-mm wafer facility.
The FDSOI planar process is claimed to have advantages over other manufacturing process variants, such as bulk planar CMOS and FinFET CMOS in terms of trade-offs between performance, power consumption and manufacturability. ST was due to begin prototyping 28-nm FDSOI in July 2012 with 20-nm FDSOI due to be ready for prototyping in 3Q13. In addition, ST has a licensing agreement with foundry Globalfoundries Inc. (Milpitas, Calif.) to be a FDSOI production and to open up the process to more customers.
ST's announcement coincides with a workshop on FDSOI being held in San Francisco alongside the International Electron Devices Meeting.
ST's FDSOI technology platform includes standard cells, memory generators, I/O cells and specific circuit blocks for analog, mixed-signal and high-speed interfaces licensable as intellectual property. The technology has been selected by ST-Ericsson for use in future mobile equipment platforms.
"By bringing FDSOI technology to manufacturing readiness, ST is again positioning itself as an innovator and leader in semiconductor technology development and manufacturing," said Jean-Marc Chery, chief technology and manufacturing officer of STMicroelectronics, in a statement. "Post-processing wafer testing has allowed us to prove the significant performance and power advantages of FDSOI over conventional technologies, building a cost-effective industrial solution that is available from the 28-nm node."
FDSOI can operate at low voltage with "superior energy efficiency" compared with bulk CMOS, ST claimed.
Chery said that ST has performed measurements on a multi-core subsystem in an ST-Ericsson NovaThor IC that combines baseband modem and application processor. The subsystem is capable of operating at 800-MHz clock frequency at 0.6 volts but can also operate at 2.5-GHz clock frequency at higher voltage, ST said. This demonstrates an extended dynamic voltage and frequency scaling (DVFS) regime.
FDSOI enables production of highly energy-efficient devices, with the use of dynamic body-bias allowing an instant switch to high-performance mode when needed and a return to reduced-leakage state for the rest of the time.
This is huge. (And it's a huge cost-saver -- IBS estimates per-die FD-SOI cost is about half that of bulk - see...
Intel looked at both...SOI and bulk...
Immersion lithography and double patterning will be used where necessary, and no extra mask layers are needed so the additional cost is only 2 - 3%. And apparently it's scalable to 14 nm!
This story is 18 months and you keep repeating the same thing (significantly lower cost) over and over again -
any real data - like comparison in $/Euro and cent?
Intel details 22nm trigate SoC process at IEDM
December 11, 2012 12:23 PM by Dick James
If more IEDM attendees had the opportunity to view the concurrent FD-SOI conference papers, acceptance would definitely have been faster. The IEDM people won't advertise the FD-SOI meeting, so unless you were already in the FD-SOI community, you'd never know. You wouldn't be able to "convert" supporters from outside, who had been attending IEDM without knowledge of FD-SOI. So, this low profile has been deliberate, for so long?
it looks like everbody's discovering now fdsoi qualities in cost saving, higher speed and power improvements. funny !
this discovery was under your eyes guys but you just didn't see it, growing for years...
Now the choice seems clear, and even bohr at the end of his career should recognise its mistake : he should have chosen fdsoi at 22nm in 2011 indeed.
ST also said of FD-SOI: Silicon-verified process technology delivers 30% higher speed and up to 50% improvement in power. This is huge. (And it's a huge cost-saver -- IBS estimates per-die FD-SOI cost is about half that of bulk - see http://www.advancedsubstratenews.com/2012/11/ibs-study-concludes-fd-soi-most-cost-effective-technology-choice-at-28nm-and-20nm/)
re: timing. Also note that the SOI Consortium as been running these symposia around major conferences for going on 4 yrs now. They are alway lively and well-attended. The papers are typically posted on fully-depleted section of their website (www.soiconsortium.org) shortly after.
No mystery or politics. Peter's analysis--that the key folks are at IEDM--is correct, as usual. His follow-on question is also easy to answer: the results presented by ST were hot off the presses (and testers). ST wasn't in position to respond to the Call for Papers early this year, when the call went out.
(Full Disclosure: I am ST's director of technical media relations)
I would take it to be not a political statement but a practical move. Many of the key engineers and engineering managers that can shape the adoption of FDSOI would be present at IEDM.
Of course you could ask why the four papers presented at the FDSOI meeting were'nt just offered up to IEDM for inclusion that meeting.
That said, the four 30-minute papers presented yesterday evening did look interesting to judge by the titles. They included one on FD 14-nm for FPGAs from Jeff Watt of Altera
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.