LONDON - Toshiba has developed a prototype spin transfer torque magnetoresistive random access memory (STT-MRAM) that it expects to be used to replace SRAM in cache memory for mobile processors within smartphones and tablet computers.
The STT-MRAM structure, the subject of a paper at IEDM 2012, taking place this week, has the lowest power consumption yet reported, and is about one-tenth that of prior reported prototypes, Toshiba said. Because of this Toshiba reckons it is the first MRAM able to compete with SRAM for cache applications and the company said it intends to accelerate R&D to that end.
The improved structure is based on perpendicular magnetization. This can be reversed at lower energy than in-plane magnetization, making it possible to program data at lower currents and fabricate smaller memory cells. The latest work by Toshiba takes the element miniaturization below 30-nm. The memory circuit has no leakage current both in operation and in standby, Toshiba said.
Toshiba STT-MRAM structure with vertical magnetization and 30-nm memory size.
The STT-MRAM structure provides an MRAM that can be of lower power consumption than its SRAM equivalent. Toshiba has also written a simulation of how such an STT-MRAM would perform as cache memory in a mobile processor application and recorded a 66 percent reduction in power consumption for standard operating functions.
The memory is the result of the "Normally-off Computing" project funded by Japan's NEDO (New Energy and Industrial Technology Development Organization). Toshiba is presenting three papers on the STT-MRAM at IEDM.
The read current is about a third of write current. The switching time depends on current, the lower current requires longer time. A long enough read could do it. But scaled down resistance goes up, slowing down read anyway.
What is the speed and current consumption for writing SST-MRAM? Write disturbance is a very serious issue for old MRAM. What is the write disturbance for present vertical SST-MRAM? Apreciate your comments.