SAN JOSE, Calif. – IBM will provide a deeper look into its work on 3-D chip stacks at the International Electron Devices Meeting (IEDM) here, detailing work on stacks of 45-nm server processors with memory and transceivers.
Big Blue has long been expected to be among the early users of 3-D stacking to pair its server CPUs with memories for performance and power advantages. It has been collaborating with Micron on the Hybrid Memory Cube, a memory stack for just such applications.
“As scaling saturates, and lithography sputters to a grinding halt, these orthogonal scaling techniques will assume even more importance and continue to keep Moore’s ‘law’ alive,” wrote Subraman S. Iyer, a senior IBM technologist in the IEDM paper to be presented Wednesday (Dec. 12).
The paper shows IBM’s road map extending from embedded DRAM to various 3-D stacks with and without interposers using face-to-face and back-to-back stacks. In a separate paper, IBM disclosed the top two layers of metal in its new 22-nm process are optimized for use with through silicon vias needed for 3-D stacks.
“Embedded DRAM, 3D stacking, interposers and wafer-to-wafer integration are intrinsic to this [IBM] roadmap,” Iyer’s paper said.
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