SAN FRANCISCO -- A panel of experts debated the future of semiconductor technology amid an array of new structures and materials, some trashing the FinFETs popularized by Intel. They made it clear there is no single road forward but rather a set of uncertain paths, each with its trade offs.
“It’s clear planar silicon as we know it ends at about the 20 nm node, then there will be a race to different architectures and materials or combinations of both,” said Suresh Venkatesan, senior vice president of technology development at Globalfoundries, moderating an evening panel at the International Electron Devices Meeting.
An IBM expert challenged that statement, showing a 10-nm planar process.
Panelists argued for an assortment of options including FinFETS, germanium, III-V materials, tunnel FETs, nanowires and fully depleted silicon-on-insulator. All sides agreed just what defines a new node is increasingly unclear.
“Any time we talk about new nodes, we should wash our mouths out with soap,” said Scott Thompson, chief technologist of startup SuVolta and a former Intel fellow. Engineers ignore traditional metrics, saying “Intel’s 22-nm node is really 26 nm, so if Intel does new math, so will we,” he said.
“The next node after 14 nm will be some small number, but there’s no real pitch scaling,” Thompson added. “Pitch scaling will slow, but we will still have smaller number nodes anyway,” he said.
Are you backing FinFETs? FD-SOI? Gemanium? Tunnel FETs? and why?
Why is AMD abandon SOI after using it for years?
AMD will therefore move on from SOI based processes next year. Kaveri that will replace Trinity will be made with 28 nanometer technology, which CTO (Chief Technology Office) Mark Papermaster confirms will be Bulk-based. The same year the cheap and energy efficient platforms Kabini and Temash will arrive, which will build on a similar 28 nanometer technology. There were not details on who will supply the process, but most likely Kaveri will be made by GlobalFoundries, while TSMC will produce Temash and Kabini.
I want to go with FD-SOI because when the substrate is fully depleted meaning no doping(theoretically) and hence the substrate will have very high resistance.
This means that the drain and source of MOS transistors can be very close as ST-Micro suggested less than 10nm (8 , 5 , ..) and still gate will have good control over the drain current which is crucial for MOS transitors to work properly.
FD-SOI will not be completely new step like Intel's 3D stacked MOS transistor architecture.
Hence FD-SOI will be more cost effective in terms of material cost of MOS transistor manufacture.
Digital MOS : FD-SOI , 3D or carbon wires will be good.
Analog MOS : ????? (for less than 10nm)
Carbon wires will be a boon for digital chips of the future with more than 10 billion switches on chip. may be good for memory as well like processor caches and SRAM kind.
IBM's left hand does not seem to know what the right hand is doing - the foundry manufacturing landscape appears in complete disarry - poor UMC "sucker" - no wait UMC figured out long before IBM that SiLK though it looked great on paper could be manufactured...
UMC licenses IBM technology for 20-nm FinFETs
www.eetimes.com › News and Analysis
Jun 29, 2012 – (UMC) has licensed technology from IBM Corp. to expedite the development of its 20-nm CMOS process, including FinFET 3-D transistors, the ...
3 big customers have committed to making foundry planar 20nm next volume node versus pick 20nm finFET (called "14 or 16nm")
Rest still deciding. There is no meaningful data anywhere on foundry Finfet so perhaps they have the same problem as Intel.
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