Both FinFETs and a competing fully-depleted silicon-on-insulator (FD-SOI) process developed by STMicroelectronics have potential to scale to the end of CMOS, argued Thomas Skotnicki, an STM fellow. In fact, STM’s approach is similar to a FinFET turned on its side, he said.
He showed a chart (below), suggesting FinFETs and FD-SOI could scale to as low as 3 and 5 nm respectively. However such small processes would challenge engineers to build a 3-nm vertical FinFET structure and a 2-nm planar FD-SOI layer, he said.
“To my eyes, the future belongs to these two,” he said.
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