LONDON – A senior engineer at FPGA vendor Altera has evaluated fully-depleted silicon on insulator (FDSOI) chip manufacturing process and concluded that the technology could have particular benefits for FPGAs. This raises the possibility that Altera could be considering replacing Taiwan Semiconductor Manufacturing Co. Ltd. (Hsinchu, Taiwan) as its foundry of choice or operating a multiple-foundry manufacturing strategy in the future.
Jeff Watt, an Altera fellow and technology development specialist,
presented An evaluation and benchmarking of 14-nm fully-depleted
technology for FPGAs at an evening symposium on FDSOI held alongside the
International Electron Devices Meeting in San Francisco.
Altera is reported to be engaged with TSMC for the 20-nm bulk planar CMOS node due to ramp in 2013 but concerns have been raised that the node will be power hungry. Grenoble research institute Leti, SOI wafer maker Soitec and IBM have been partners with STMicroelectronics NV (Geneva, Switzerland) in the development of the FDSOI process, and ST has added a licensing deal with Globalfoundries Inc. (Milpitas, Calif.) that could increase manufacturing capacity. TSMC is not known to be working on FDSOI but has indicated it plans a rapid transition to a 16-nm FinFET manufacturing process as its next-generation technology in 2014.
In his presentation Watt concluded that planar FDSOI has advantages for ICs in general but has particular benefits for FPGA circuits. His presentation made comparisons between bulk planar CMOS at 28-nm and FDSOI planar CMOS at 14-nm suggesting that Watt has adopted the convention that the next FDSOI node after 28-nm should be labeled 14-nm FDSOI (see FDSOI roadmap renames next node as 14-nm).
Watt said in his presentation that 14-nm FDSOI could give a 35 percent performance improvement compared with 28-nm bulk planar CMOS at the same switching power or a 32 percent lower switching power at the same delay time. Watt also showed how the use of body bias to effect power/delay trade-off customization over a wide range could be attractive to the FPGA maker.
Altera's interest could be a possible fall out of supply problems experienced by customers of 28-nm bulk CMOS manufacturing at TSMC during 2012. There was speculation at that time that Altera might turn to Intel as a foundry supplier that could offer leading-edge FinFET manufacturing process technology. If Altera opts to build some FPGAs on FDSOI it would likely be supplied by Globalfoundries as ST only has pilot line capability at its wafer fab in Crolles.
TSMC has reportedly secured large orders for FPGAs to be made using next-generation 20-nm bulk planar CMOS from both Altera and its rival Xilinx. Altera was rumored to be the first company to commit to TSMC's 20-nm planar bulk CMOS process, which is expected to ramp in 2013. In addition both Altera and Xilinx are thought to be interested in multi-chip packaging using TSMC's CoWoS (chip on wafer on substrate) process but TSMC has yet to begin volume production of 20-nm.
However, a dual-foundry or multiple foundry manufacturing strategy could create difficulties for Altera. One of the benefits of staying loyal to one foundry is early access to process technology, something that is vital to FPGA vendors. There could be concerns that TSMC would provide better support and access to the customer that is 100 percent loyal.
Related links and articles:
Full slide decks from FDSOI symposium available at:
Word is Altera told TSMC they see no value in "20 nm FinFET" called "16nm node"
16nm is a Die size increase from 20 nm SOC and no power savings since FDSOI has body bias (key in FPGA) and no Body Bias in FinFETs.
Altera will use TSMC 20nm and look for other options.
My understanding is that 14-nm FDSOI is the new name for what was 20-nm FDSOI.
And that it will be offered in 2014 at approx. the same time as 14-nm FinFETs from Intel, the 14XM process from Globalfoundries and 16-nm FinFET process from TSMC.
1. 14nm SOC is equals "20nm density design rules"
2. 16nm TSMC finFET equals 20nm density design rules"
3. 14nm Global FinFET is equals "20nm density design rules"
4. 10nm TSMC equals 14nm density design rules (S=0.7 scale factor from 20nm).
Business orders are are for 20SOC (planar). No business model to redesign all the functional block IP to finFET or FDSOI at same density.
10nm will be SOI for all process variants HP/LP