Schematic representation of retrograde well engineering (gate dielectric omitted). (Source: Intel)
The SuVolta PowerShrink transistor is very similar to FD-SOI transistor. FD-SOI uses a SOI wafer with 10- to 15-nm layer of silicon over a buried layer of oxide and prepares planar transistors in that ultra-thin region. The SuVolta device creates a 5-nm thick channel immediately below the surface of a silicon wafer by implanting a series of dopant layers beneath the channel. The implants form a buried junction that when properly biased deplete the active region of the channel. The result is a device that exhibits the low leakage current, high mobility, a low threshold voltage variation but on a conventional low-cost silicon wafer.
This is essentially the same as the SSRW approach that has been investigated by several chip makers, including Intel and IBM.
Fujitsu Semiconductor became SuVolta's first licensee for its DDC technology in June 2011. Since then, they have worked to bring DDC technology to the 65- and 55-nm process nodes. In joint paper at IEDM, the partners compared the same circuits fabricated in Fujitsu Semiconductor’s standard CMOS process and those using DDC technology. They said the results demonstrated a 47 percent power reduction at matched performance when running the DDC technology with a supply voltage of 0.9-V. DDC is also able to be run considerably lower than that.
Fujitsu is reportedly exiting the semiconductor business, and another partner could potentially help SuVolta to demonstrate the effectiveness of its approach at the leading-edge of semiconductor manufacturing.
Asked if it is working with SuVolta on SSRW technology, a Globalfoundries spokesman said via e-mail: "The SSRW device technology has been published by many researchers in the past ten years. We are evaluating multiple SSRW options within and outside of the Globalfoundries R&D ecosystem. Our priority is to pick the best approach that offers value to our customers, but at this time we are not prepared to discuss any further details."
Related links and articles:
MOS scaling: Transistor challenges for the 21st century by Thompson, Packan, Bohr of Intel
Foundries not dead, just evolving, says Globalfoundries CEO
SuVolta reports 65nm parameter results at IEDM
Fujitsu said to want out of chip business
ST opens up 28-nm, 20-nm FDSOI with GlobalFoundries
IEDM: SuVolta transistor operates down to 0.4-V