The folks at Aldec asked me to "spread the word" regarding the availability of their most-viewed white papers on verification as follows:
Those Pesky Interfaces…
SystemVerilog Interfaces offer some very interesting features for both hardware designers and verification engineers. Unfortunately, they are also one of the most misunderstood SV constructs. This document tries to explain interfaces, paying special attention to the virtual interface concept used in popular UVM library. Download paper
Debugging SCE-MI Co-Emulation
Learn about Aldec’s debugging environment for SCE-MI co-emulation that provides 100% signal visibility of the design running in an FPGA-based emulator. Download paper
Randomization and Functional Coverage in VHDL
Modern digital designs reach the scale of complete systems and require support of Constrained Random Test and Functional Coverage in verification. Although VHDL does not have built-in, direct support for those methodologies, there are solutions that allow their quick implementation in your testbench. Download paper
DO-254 - Increasing Verification Coverage by Test
Verification coverage by test is essential to satisfying the objectives of DO-254. However, verification of requirements by test during final board testing is challenging and time-consuming. This white paper explains the reasons behind these challenges, and provides recommendations how to overcome them. The recommendations center around Aldec’s unique device testing methodology that can significantly increase verification coverage by test. Download paper
Clarifying Language Methodology Confusion
Addresses the challenges of changing languages, methodologies and tools, that are faced when working with large, modern FPGA designs. Download paper
Click Here to view all of Aldec's whitepapers.
If you found this article to be of interest, visit Programmable Logic Designline
where – in addition to my Max's Cool Beans
blogs – you will find the latest and greatest design, technology, product, and news articles with regard to programmable logic devices of every flavor and size (FPGAs, CPLDs, CSSPs, PSoCs...).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here
to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).