With DesignCon 2013 approaching, I've got 10 tech questions I'd like to get answered. (We'll present Rick's first five today; five more next week - Editor.)
A big reason I'm going to the show is to keep pace with chip interfaces stepping up from five to 25 Gbits/s, boards revving from 10 to 100 Gbits/s and systems gearing up for a shift to 400 Gbits. Accordingly, my umbrella question is: What are the latest gnarly issues in signal integrity? (See Colin Johnson's Stars of DesignCon: Signal integrity in tricked-out, high-speed interconnects for some answers.)
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I know at these data rates, PCB traces start to act like radios. How do
you tune them down? I note organizers created a half day tutorial on
DesignCon brings out the SI experts each year for a panel thrashing out the current issues. In addition, one of my go-to SI guys, consultant Eric Bogatin, will share his thoughts. (Use Chrome for the session links -editor.) Experts from Intel will join others in a separate session on both signal integrity and the newer related field of power integrity—which leads me to my second question (click to next page).
Rick, thanks for the link. I am caught up with emails from the holiday break and found the work of Prof. Joungho Kim of KAIST in Phil Garou's article:
The link above describes some work of KAIST on glass interposers vs. Silicon. Interesting thing is that it is also the first instance where I see optical wave guides in the context of 2.5D/3D stacking.
Rick, I am looking forward to your next five... I would be curious to know what KAIST is going to present on 3D Stacks (haven't seen much from them on this).
Regarding 400Gbits systems, it could herald the beginning of the end of Copper chassis-to-chassis interconnects as we know it; for sure it will restrict the application to within cabinet interconnects. But there are still challenges on motherboards -need better dielectric materials which will drive up the costs, not to mention power and signal routing and signal integrity.
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