Breaking News
News & Analysis

DesignCon's 5 Toughest Tech Questions

12/28/2012 05:40 PM EST
6 comments
NO RATINGS
Page 1 / 5 Next >
More Related Links
View Comments: Newest First | Oldest First | Threaded View
docdivakar
User Rank
Author
re: DesignCon's 5 Toughest Tech Questions
docdivakar   1/3/2013 5:34:13 PM
NO RATINGS
Rick, thanks for the link. I am caught up with emails from the holiday break and found the work of Prof. Joungho Kim of KAIST in Phil Garou's article: http://www.electroiq.com/blogs/insights_from_leading_edge/2012/12/iftle-126-2012-gatech-interposer-conference-part-2.html?cmpid=EnlAPDecember192012 The link above describes some work of KAIST on glass interposers vs. Silicon. Interesting thing is that it is also the first instance where I see optical wave guides in the context of 2.5D/3D stacking. MP Divakar

rick merritt
User Rank
Author
re: DesignCon's 5 Toughest Tech Questions
rick merritt   1/2/2013 9:40:48 PM
NO RATINGS
KAIST has two 3-D papers at the event. One on TSV failures and the other looks more interesting on 2.5-D GPU and memory. See http://www.designcon.com/santaclara/conference/tracks.php?session_id=239

docdivakar
User Rank
Author
re: DesignCon's 5 Toughest Tech Questions
docdivakar   1/1/2013 10:12:59 PM
NO RATINGS
Rick, I am looking forward to your next five... I would be curious to know what KAIST is going to present on 3D Stacks (haven't seen much from them on this). Regarding 400Gbits systems, it could herald the beginning of the end of Copper chassis-to-chassis interconnects as we know it; for sure it will restrict the application to within cabinet interconnects. But there are still challenges on motherboards -need better dielectric materials which will drive up the costs, not to mention power and signal routing and signal integrity. MP Divakar

rick merritt
User Rank
Author
re: DesignCon's 5 Toughest Tech Questions
rick merritt   12/29/2012 9:43:43 PM
NO RATINGS
What are your burning questions in high-speed design? Join the conversation.

Most Recent Comments
michigan0
 
SteveHarris0
 
realjjj
 
SteveHarris0
 
SteveHarris0
 
VicVat
 
Les_Slater
 
SSDWEM
 
witeken
Most Recent Messages
9/25/2016
4:48:30 PM
michigan0 Sang Kim First, 28nm bulk is in volume manufacturing for several years by the major semiconductor companies but not 28nm FDSOI today yet. Why not? Simply because unlike 28nm bulk the LDD(Lightly Doped Drain) to minimize hot carrier generation can't be implemented in 28nm FDSOI. Furthermore, hot carrier reliability becomes worse with scaling, That is the major reason why 28nm FDSOI is not manufacturable today and will not be. Second, how can you suppress the leakage currents from such ultra short 7nm due to the short channel effects? How thin SOI thickness is required to prevent punch-through of un-dopped 7nm FDSOI? Possibly less than 4nm. Depositing such an ultra thin film less then 4nm filum uniformly and reliably over 12" wafers at the manufacturing line is extremely difficult or not even manufacturable. If not manufacturable, the 7nm FDSOI debate is over!Third, what happens when hot carriers are generated near the drain at normal operation of 7nm FDSOI? Electrons go to the positively biased drain with no harm but where the holes to go? The holes can't go to the substrate because of the thin BOX layer. Some holes may become trapped at the BOX layer causing Vt shift. However, the vast majority of holes drift through the the un-dopped SOI channel toward the N+Source,...

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
Like Us on Facebook
EE Times on Twitter
EE Times Twitter Feed