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DesignCon's 5 Toughest Tech Questions

12/28/2012 05:40 PM EST
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rick merritt
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re: DesignCon's 5 Toughest Tech Questions
rick merritt   12/29/2012 9:43:43 PM
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What are your burning questions in high-speed design? Join the conversation.

docdivakar
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re: DesignCon's 5 Toughest Tech Questions
docdivakar   1/1/2013 10:12:59 PM
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Rick, I am looking forward to your next five... I would be curious to know what KAIST is going to present on 3D Stacks (haven't seen much from them on this). Regarding 400Gbits systems, it could herald the beginning of the end of Copper chassis-to-chassis interconnects as we know it; for sure it will restrict the application to within cabinet interconnects. But there are still challenges on motherboards -need better dielectric materials which will drive up the costs, not to mention power and signal routing and signal integrity. MP Divakar

rick merritt
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re: DesignCon's 5 Toughest Tech Questions
rick merritt   1/2/2013 9:40:48 PM
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KAIST has two 3-D papers at the event. One on TSV failures and the other looks more interesting on 2.5-D GPU and memory. See http://www.designcon.com/santaclara/conference/tracks.php?session_id=239

docdivakar
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re: DesignCon's 5 Toughest Tech Questions
docdivakar   1/3/2013 5:34:13 PM
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Rick, thanks for the link. I am caught up with emails from the holiday break and found the work of Prof. Joungho Kim of KAIST in Phil Garou's article: http://www.electroiq.com/blogs/insights_from_leading_edge/2012/12/iftle-126-2012-gatech-interposer-conference-part-2.html?cmpid=EnlAPDecember192012 The link above describes some work of KAIST on glass interposers vs. Silicon. Interesting thing is that it is also the first instance where I see optical wave guides in the context of 2.5D/3D stacking. MP Divakar

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