With DesignCon 2013 approaching, I've got 10 tech questions I'd like to get answered. (We'll present Rick's first five today; five more next week - Editor.)
A big reason I'm going to the show is to keep pace with chip interfaces stepping up from five to 25 Gbits/s, boards revving from 10 to 100 Gbits/s and systems gearing up for a shift to 400 Gbits/s. Accordingly, my umbrella question is: What are the latest gnarly issues in signal integrity? (See Colin Johnson's Stars of DesignCon: Signal integrity in tricked-out, high-speed interconnects for some answers.)
[Click here to register for DesignCon 2013, Jan. 28-31 at the Santa Clara Convention Center. Options range from an All-Access Pass to Free Expo Admission, which includes the option to attend a dozen tech training sessions.]
I know at these data rates, PCB traces start to act like radios. How do
you tune them down? I note organizers created a half day tutorial on
DesignCon brings out the SI experts each year for a panel thrashing out the current issues. In addition, one of my go-to SI guys, consultant Eric Bogatin, will share his thoughts. (Use Chrome for the session links -editor.) Experts from Intel will join others in a separate session on both signal integrity and the newer related field of power integrity—which leads me to my second question (click to next page).