Got DesignCon questions? Last week, I put forth five questions I'd like answered at the electronics industry's go-to conference covering all aspects of chip, board, and system design. Here are five more:
[Click here to register for DesignCon 2013, Jan. 28-31 at the Santa Clara Convention Center. Options range from an All-Access Pass to Free Expo Admission, which includes attendance at a dozen tech training sessions.]
When do we get to 440-Gbit/s Ethernet?
Later this year, a group of Ethernet experts will convene to start work on a next big step for this dominant network technology—a move to a 400 Gbit/s standard. To get there at all requires 28 Gbit/s serdes just now coming to market. To get there with some elegance will take signaling circuits that run faster than 40 Gbits/s, something that doesn’t exist today.
Can we get there? How and when? These are top questions to get perspective on at DesignCon. I hope to catch up with Adam Healy, a veteran SerDes expert with LSI Corp. Healy will present at a session about modulation schemes for just such products. He'll be followed by a talk from Altera on channel issues in the same beyond-25G territory.
In a related paper, IBM will talk about terahertz-class designs based on chain ganging multiple high speed serdes together for its top servers. It may not relate directly to 40G+ work, but I guarantee it will be interesting and the engineers there will have some thoughts on the topic.
Links to sessions mentioned above:
Beyond 28G paper on modulation by LSI
Beyond 25G: Channel paper by Altera
IBM paper on multiple high speed serdes “terabit class” design
Modeling at rates beyond 10 GHz