DesignCon, coming Jan. 28-31 at the Santa Clara Convention Center, is positioned as the leading live event for chip and systems designers and software developers. It's got keynoted from top engineers at Cisco, NVidia, and National Instruments, as well as a wealth of tech training sessions.
In advance of the show, DesignCon is offereing a free pass to the show-floor exhibits.
The free pass comes with an option to attend a dozen vendor-sponsored education and training classes.
If you're in interested in attending all the sessions, there are a variety of paid options, including an all-access pass.
DesignCon Registration (direct to registration page link):Click here to register for DesignCon 2013, Jan. 28-31 at the Santa Clara Convention Center. Options range from an All-Access Pass to Free Expo Admission, which includes the option to attend a dozen tech training sessions.
Monday, January 28: Challenges and Solutions in Characterizing a 10Gb Device (Agilent) PCI Express 3.0 Characterization,Compliance, and Debug for Signal Integrity Engineers (Teledyne LeCroy)
Tuesday, January 29: Synchronous Time and Frequency Domain Measurements Using a Digital Oscilloscope (Rohde & Schwarz) Ensuring Validation & Analysis of Complex Serial Bus Link Models (Tektronix) USB 2.0 Compliance Testing (Rohde & Schwarz) Phase Noise and Jitter Measurements (Rohde & Schwarz) True Differential S-parameter Measurements / Rohde & Schwarz Synchronous Time and Frequency Domain Measurements Using a Digital Oscilloscope (Rohde & Schwarz) USB 2.0 Compliance Testing (Rohde & Schwarz) Phase Noise and Jitter Measurements (Rohde & Schwarz) True Differential S-parameter Measurements (Rohde & Schwarz) Ensuring Validation & Analysis of Complex Serial Bus Link Models (Tektronix) Advances in 3D SI Simulations of Interconnects for Chip/Package/PCB (CST of America Inc.)
Wednesday, January 30: Making DDR4 Work For You (Agilent) Debugging to Find the Root Cause of Compliance, Limit or Mask Test Violations (Teledyne LeCroy)
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for todays commercial processor giants such as Intel, ARM and Imagination Technologies.