Like many high-speed design experts, Donald Telian is exploring the small, hidden places where problems hide. His DesignCon 2013 paper talks about losses in vias and via models.
“Most people have been staring at channels and long runs but with back drilling, vias have been problematic for a long time,” said Telian a signal integrity consultant for SI Guys (Oakhurst, Calif.). “It may be less than a tenth of a percent of the channel length, but it’s an important area,” he said.
Looking at the big picture, this DesignCon is really all about figuring out how to make the shift from 10 to 25G products, said Telian, echoing McMorrow and others. That involves work both in the passive channel and the silicon, said Telian who designed signal integrity for the original PCI bus.
Some of the new pc board materials hold promise of cutting losses nearly ten-fold, he said. As for the chips, “gates are still essentially free, and that’s turning into some really good equalization,” he added.
Engineers are moving to techniques such as three taps of decision feedback equalization to capture signals. “We started in the transmitter, now we’ve jumped to the receiver and that takes more intelligence because you are flying blind, but that’s where the action is today,” he said.
Donald Telian’s paper on vias