LONDON – STMicroelectronics is in discussions with Globalfoundries Inc. on a transfer of fully depleted silicon on insulator (FDSOI) manufacturing process technology for volume production in 2013, according to a senior executive at ST.
ST claims that at 28-nm, its FDSOI process can provide 30 percent more performance than bulk 28-nm CMOS at the same power consumption, or, alternatively, can provide as much as a 50 percent saving in dynamic power consumption at the same performance. This is because FDSOI allows the use of voltages down to 0.6-V whereas bulk CMOS only goes down to about 0.9-V, said Joel Hartmann, executive vice president of front-end manufacturing and process R&D, for the digital sector at ST.
ST has produced a technical video that outlines the technical advantages of the process (see below)
Multiple companies have been accessing a physical design kit for 28-nm FDSOI that has been made available through the SOI Consortium, Hartmann said. However, to commit to the process they want to be assured that manufacturing capacity will be in place when they need it, hence the need to press forward with Globalfoundries.
"We have an MoU [memorandum of understanding] with Globalfoundries. Right now we are discussing the details of the contract," said Hartmann. Globalfoundries signed up in principle in June 2012 to be a source of FDSOI chips both for ST and for other customers. For prototypes and initial volumes ST is already able to manufacture chips using the 28-nm FDSOI process at its pilot fab in Crolles, France.
Hartmann said Fab 1 in Dresden, Germany, would be a logical place for Globalfoundries' to host FDSOI as it is already the where the foundry manufactures 32/28-nm bulk CMOS. "If we start this month or in February Globalfoundries could be in production in the fourth quarter of 2013," said Hartmann.
Hartmann acknowledged that the raw wafer cost for a silicon-on-insulator wafer is about two to three times that of a standard silicon wafer. But the FDSOI manufacturing process is simpler, he said, which saves cost and improves yield. "FD-SOI process cost is 10 to 12 percent cheaper than bulk. This will allow us to fully compensate extra cost of SOI substrate when in high-volume manufacturing," said Hartmann.
ST subsidiary ST-Ericsson has announced a modem-application processor, the L8580, manufactured using 28-nm FDSOI, which will be available in sample quantities in 1Q13. A senior engineer at FPGA vendor Altera Corp. has evaluated FDSOI and concluded that the technology could have particular benefits for FPGAs. "Internally at ST we are also looking to use the process for consumer applications where power consumption is important," said Hartmann. Hartmann declined to disclose which products or product lines ST would be transferring to FDSOI manufacturing.
The video below has been produced by STMicroelectronics. It lasts about 8 minutes and provides a useful introduction to the FDSOI process and its features in comparison with bulk CMOS.
Quite nice video, is really intuitive and appealing. Indeed the body bias voltage benefit of FDSOI will be quite interesting for FPGAs, Altrea's interest makes sense in perspective of their Programmable power.
What surprises me that they have a roadmap going well upto 10nm. What are the pros of Trigate/Finfet technology that majority of industry is going/prefering that direction after 28nm?
I touch on this in my London Calling column: http://www.eetimes.com/electronics-news/4405296/London-Calling-What-next-for-big-little
But I do wish that companies would not succumb to temptation of describing two physical cores as a quad-core.
You could equally well say that because the same processor can run two applications it should be called a dual-core, or if you are talking about 21 applications a vingt-et-un-core.
In June 2012 SOI conference Soitec announced high volume manufacturing of 28-nm SOI wafers with 12-nm SOI thickness and 25-nm buried oxide. In order to suppress the transistor leakage current or short channel effect, however, ST’s FDUTBB requires an extremely thin 7nm or 0.7A (angstrom) that is less than 1A channel thickness confined by the 25-nm buried oxide. The question I have is how the wafers with initial 120A channel thickness were reduced to 0.7A in volume manufacturing by ST? ST video claims that its UTBB behaves like a vertical double gate. ST’s UTBB consist of two transistors: the top transistor having the proven HK metal gate very reliable used today in semiconductor industry but the bottom transistor having the Si substrate gate and the 25-nm thick buried gate oxide is totally new and unproven in reliability, performance, and not adopted by semiconductor industry. A number of interface states could be generated at the thin Si channel- the buried oxide interface. Subsequently, electrons and holes could be trapped at the interface, adversely impacting device reliability and performance. Besides, a large substrate bias voltage is required across the 25-nm buried oxide to control the threshold voltage, Vt of the top transistor, but it also could change the source and drain voltages as well. IBM’s new roadmap for FDSOI down to 14-nm node doesn’t include UTBB. Why IBM has not manufactured FDSOI at any technology node yet? I would like to see ST’s 28-nm transistor data published so that we can compare with the 28-nm planer bulk data that are published widely. If the UTBB is in production ready, such transistor data should be readily available. Skim
Thank you Mr. Kim for your comments. As I think I had shared with you on another blog:
- Thin silicon thickness: We are moving from a raw 12nm thick silicon film (=120A, +/- 5A) to a final film of 7nm (=70A) under the transistors. This is a perfectly repeatable process and is already qualified for production at ST.
- The body-bias capability, or more accurately back bias (because biasing is done on the back face of the transistor), is a way to electrically control the Vt of the device by controlling of the polarization of the wells. Conceptually, it is like having the planar transistor controlled by two gates: the real "classical" gate, we build with a HKMG, gate-first manufacturing approach, and a virtual gate (represented in the video with a transparent gate below the transistor) that controls the transistor through biasing. Thanks to the thickness of the Buried Oxide (BOX), we can apply biasing voltages up to 3V.
- Advantages of UTBB FD-SOI: You should read A. Khakifirooz at al., “Extremely thin SOI for system-on-chip applications”, CICC 2012. This paper, written by authors from IBM, STMicroelectronics, LETI, Renesas, and GLOBALFOUNDRIES, should convince you of the advantages.
- 28nm FD-SOI technology details: This information has recently been published at IEDM 2012 (F. Arnaud et al., “Switching Energy Efficiency Optimization for Advanced CPU Thanks to UTBB Technology”).
Most important, to prove manufacturability, the recent announcement from ST-Ericsson about their NovaThor L8580 product, which was demonstrated at CES, is capable of running its eQuad ARM cores up to 2.8GHz, while still fitting a mobile smartphone thermal footprint and proving (if needed) the potential and the maturity of FD-SOI technology.
Giorgio Cesana, STMicroelectronics
I would like to thank Mr. Cesana for pointing out: 6nm is 60A, not 0.6A. Since MR. Cesana’s comments are mostly on UTBB, I will respond to FDUTBB. Remember FD UTBB and FDSOI are not the same.
ST video claims that its UTBB behaves like a vertical double gate. It doesn’t. The double gate is an ideal transistor structure having common gates and common source /drain, thus good control of electrostatics and doubling the transistor on-current, Ion. ST’s UTBB has common source and drain, but has two independent gates consisting of two transistors, the top transistor having the proven HK metal gate very reliable used today in semiconductor industry but the bottom transistor having the Si substrate for a gate and the 25-nm thick buried oxide for gate oxide, sharing 7nm channel is totally new and unproven in reliability, performance, and not adopted by semiconductor industry. During UTBB operation a positive 3V is applied to the bottom gate to control Vt of the top gate. How much the transistor I-on is improved by the positive 3V applied to the bottom gate is not shown. Furthermore, some of channel electrons could drift toward the buried oxide and become trapped inside under the 3V positive bias field during UTBB operation, especially near the source region where electron velocity is very slow. Also, a number of interface states could be generated at the thin Si channel-the buried oxide interfaces, and the channel electron mobility could be degraded due to enhanced scattering at the channel-buried oxide interface, resulting in reduced I-on. These could adversely impact UTBB reliability and performance. These phenomena are unique to FD-UTBB because planer bulk, FinlFET, and FDSOI are not substrate biased or grounded during device operation.
Mr. Ceaena has six comments. I give my answers accordingly:
-Thin silicon thickness: Soitec can’t deliver SOI thinner than 12nm for Bulk 28nm technology today. Can you move from a raw 12nm thick silicon film (+/-0.5nm) to final film of 7nm under the transistors reliably and uniformly across 300mm wafers in volume manufacturing? The process looks to me for test chip or test wafer process. Is the process can be also applicable to 20/22nm nodes that require approximately 5nm SOI thin channel?
-Next three comments are related to UTBB. Pease see my blog posted: ST plans for Dreden FDSOI production. I was at the 2010 and 2012 IEDM presentations. These papers claimed FDSOI technology would present major advantages over planer bulk CMOS in performance and manufacturing. In this sense these papers became an old FDSOI and UTBB papers because 28/32nm planer Bulk is manufactured by Intel, TSMC, Samsung, UMC and others for more than two years, and Intel’s 22nm FinFETs are in high volume manufacturing over a year, but FDSOI and UTBB are not in volume manufacturing at any node yet. If a thinner than what Soitec can deliver, you have to do the same thing ST did above. All the experimental data collected are statistical nature based on SPICE and TCAD simulations. No single transistor characteristics are shown because SOI thickness of 5nm required for 20/22nm FDSOI and UTBB can’t be built except possibly in test chips or test wafers.
-The last item: I am somewhat confused. FDSOI and FDUTBB are not the same. The 28nm FDSOI is not manufacturable today while ST claims the 28nm UTBB process is qualified for production. However, No UTBB transistor characteristics such as VT, Id/Vg, Id/Vd are published. In contrast, a large number of such BULk 28nm transistor data are available. How transistor performance can be compared without such data?. I complained about this subject at 2012 IEDM, see my blog posted “IC Manifacturing Showdown”. Skim