SAN JOSE, Calif.--Ultra low power microcontrollers will get a new yard stick by this fall from the Embedded Microprocessor Benchmark Consortium. EMBC’s ULP benchmark will measure energy consumed running workloads for chips targeting portable medical devices, security systems, building automation, smart meters and other devices that aim to run for years on a single battery.
“When these devices are in real low power modes it is not just about their execution times but how well they use sleep modes, how often they have to wake up processors and how much energy they waste,” said EEMBC President Markus Levy. “We will simulate measurements over a year or even a decade,” he said.
Just how the benchmark will operate is still under discussion by a working group headed by Horst Diewald, chief architect of MSP430 microcontrollers at Texas Instruments. Other companies represented in the group include Analog Devices, ARM, Microchip, Renesas and STMicroelectronics.
Atmel, Energy Micro and Silicon Labs have joined EMBC also are members of the working group. Lockheed Martin is an observer on the effort and an EMBC board member.
“We would like to have more system companies participate at least as advisers,” said Levy. “Once we get our first phase out, we may get more participants from systems companies."
Membership to EMBC costs $7,500 for the first year. The ULP group hopes to have an alpha version of its benchmark out to members before April and a publicly available version in the fall.
Could energy consumption of electronic devices be further reduced by having peripherals which activate the sleeping processor rather than the processor continuously polling the external environment? A remote switch, for example, requires no current flow when off and yet instantly alerts the processor when needed. If the remote devices connect to identifiable input lines, the line which is activated could also identify the action required.
Ultra low power processors are in demand not only in medical application but also in general application. I believe the focus shall be more than just power management (aka sleep mode). The power consumption of full load shall be one of the many considerations.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.