SANTA CLARA, Calif. – Cisco Systems is prototyping silicon photonics using 2.5-D silicon interposers, according to a senior engineering executive in a keynote at DesignCon here. The communications giant is one of a handful of companies trying to harness the technology to drive down the costs of next-generation networks.
“The convergence of optical and semiconductor ecosystems will have a huge impact for networking at 40 and 100 Gbits/second and beyond,” said Bill Swift, who leads Cisco’s transceiver and module group.
Swift showed a rough diagram (below) of a 2.5-D chip that included a laser light source, optical lenses and isolators along with what appeared to be a CMOS modulator and multiplexor. “This is stuff we are working on now, and I find it very exciting,” he said.
He declined to comment on reports the company will ship this year samples of 100G silicon optical modules based on the LX4 standard. Cisco bought silicon-photonics startup Lightwire (Allentown, Penns.) in February 2010 for $271 million.
Click on image to enlarge.
Lightwire’s first generation product used wavelength division multiplexing to put four 25G channels over a single fibre, sources said. Along with startup Luxtera, it is pushing for use of advanced coding techniques such as eight-level pulse amplitude modulation to get to 50G serial links.
Among Cisco’s competitors, Intel announced earlier this monthit is shipping engineering samples of 100G silicon photonics modules. Startups Luxtera and Kotura plan to ship 100G silicon photonics modules in 2014. Intel is using CMOS for all the major components including the laser light source; Luxtera and Kotura use external lasers.
Swift said 3-D ICs will reduce chip power and accelerate integration. The 2.5-D version using silicon interposers is the latest version of a technology that’s been around for years, he said.
"In the 1990’s, I used a pcb interposer because I got my BGA wrong, now we can use it to put multiple die on silicon,” he quipped.
Convergence of CMOS and optics will drive next-gen nets, Swift said.
here is some thing that may interest people as possibly some thing that may be ahead of this.
Opel Laser Uses POET Optoelectronic Platform
The III-V gallium arsenide (GaAs) based monolithic platform could change the roadmap for smartphones, tablet and wearable computers
Opel's U.S. affiliate, Odis Inc. has produced an integrated laser device in its Planar Optoelectronic Technology (POET) process.
The laser enables high-performance devices fusing optical and electronic devices together on a single chip.
After years of development, the fabrication of the first Vertical Cavity Laser, (VCL) utilising Odis'patented POET GaAs III-V technology is a significant success.
Incremental progress over the years has led to what many consider to be the next phase of semiconductor development which is to surpass the capabilities of complementary metal oxide semiconductor (CMOS) technology for the next generation of high speed low power applications.
The POET advantage is the merging of optical devices into the growth and fabrication that supports complementary HFET analogue and digital functions.
The intimate connections between diverse device types enables novel gate designs which dramatically reduce the power consumed in the opto-electronic (OE) and electro-optic conversions. The VCL has the small footprint required for dense circuit layout and enables vertical connections from anywhere in the circuit plane to fibre or to other stacked chips.
Moving forward, development will lower the threshold current, increase the output power and optimise the in-plane version of the VCL. Also, the complementary transistor circuit capability will be enhanced by reducing the feature size to the 100 nm scale incorporating Odis' new self-aligned contact technology.
With transistor cutoff frequencies around 38 GHz for a 0.7µm gate, the scaling is expected to produce 260 GHz transistors with big improvements in circuit speed.
First reported bonded laser on SOI was a joint project that Intel and UCSB worked on a couple of years ago. Some collaborating European groups independently developed the same thing but with a different III-V active material nearly the same time. I remember Intel&UCSB published their results in a fast review cycle journal to beat their opponents. Bonded lasers in principal suffer from lower performance by using SOI waveguide as external lasing resonator, let alone the complexity in processing (but which can be conquered) and size mismatch between InP wafers and Si wafers. But I heard some improvement recently. Intel didn't push very hard in fully monolithic integration of photonic components and CMOS circuits for TIA and laser driver. Luxtera spent a ton of money and nearly a decade on incorporating photonic components in a legacy 130nm line of Freescale which is only good for upto 10G. 25G TIA&driver needs at least 65nm which need too much design rule and library changes to have photonics in. This is much harder than mixing digital and analog circuits which still meets troubles from time to time. It may worth doing, but you definitely need someone with deep pocket.
Sounds like pretty disruptive technology if they can pull it off in mass production...would anyone be interested in discussing it at Grenoble emerging technologies symposium, details at www.cmosetr.com? planning a panel discussion on this topic, firstname.lastname@example.org
@Divakar: Thanks for the SDN link. Yes, a potentially huge disruption for Cisco!
Swift was so vague it's hard to tell exactly what Cisco is planning with 2.5-D and optics but your guess is more technically informed than mine!
Unfortunately, the integration of these different optical components like lens and laser can be done in a identical thus cost effective way like 2.5D electronics. Different bonding/soldering techniques and tolerances exist for different components, i.e. laser requires sub-micro placement accuracy. So up to now, it's merely a reduced scale of optical packaging on Si instead of on submount.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.