SANTA CLARA, Calif.--Cultural complacency and "uncomplaining"
engineers are stunting EDA tool investment and preventing IC
companies from keeping up with quickening design complexity, a
senior engineering manager at chip vendor Nvidia Corp. said Tuesday (Jan. 29).
"Engineers don't complain enough," said Jonah Alben, Nivida's senior vice president of engineering, said during a keynote address at the DesignCon conference here.
"Engineers like myself tend to ultimately figure out a way to live
with whatever environment they're put into," he said. "They don't
speak up when everyone else is speaking up in the company about what
we want to see in the next-generation product."
That, combined with "cultural complacency"--struggling to navigate new
daily challenges and manage priorities--usually prompts companies to
tamp investment in EDA tools while under-staffing their
Nvidia engineering VP Jonah Alben after his DesignCon keynote.
"Despite the value of EDA, in general companies tend to under-invest
in it, and I'll put my company into that bucket," Alben said.
This is happening at time when there's a widening gap between the
growth rate of chip complexity and the ability of tools to, for
example, simulate them efficiently, Alben said.
"The problem is we're in this multicore era of CPU. It's good for
throughput...but for logic simulators...it's not been great era for
them in terms of their intrinsic speed of simulation," he said.
Alben cited the example of a 2008 CPU design that today would be
four times as big and complex, while simulation runs would takes
In the past, an engineer might have been running two hours worth of
simulation tests to find bugs.
"On any given day, you can find a bug, fix a bug. Now they might be
looking at eight hours to get feedback," he said. "This is
definitely a significant problem we're looking at, and it's only
going to get worse as we move forward."
As our products grow, the simulations to verify them grow exponentially. Fortunately, those new more powerful chips are now running our computers. The only way to keep ahead is to partition the design and simulate smaller blocks first. Once that is done, you can simulate the entire chip using functional models instead of full designs of the blocks. Timing analysis is still the big issue at the end of the design.