LONDON – Warren East, CEO of processor IP licensor ARM, says the company stands ready to help STMicroelectronics make a success of its fully-depleted silicon-on-insulator (FDSOI) chip manufacturing process, but that it is up to ST to make the process more widely available.
Speaking to EE Times in a discussion of ARM's 4Q12 and full year financial results East said of FDSOI: "We think it is pretty good technology and we would encourage ST to proliferate it. The physical IP we need to create is essentially the same [as for bulk CMOS]."
FDSOI has emerged at the 28-nm node as a potential chip manufacturing alternative to bulk planar CMOS, which is being pushed to 20-nm by foundries such as Taiwan Semiconductor Manufacturing Co. Ltd. and Globalfoundries Inc. Both those foundries then propose to move rapidly to FinFET-based processes at nodes labeled 16-nm and 14-nm, respectively.
Some observers have argued that 20-nm bulk planar CMOS will not produce significant power savings while being hard to manufacture. The FinFET processes, where transistors are created in fins standing proud of the silicon surface, could be even more complicated to make and harder to yield.
However, the FDSOI process developed by STMicroelectronics does not yet have any high volume or foundry manufacturing capacity in place. The earliest that any could come on-stream would be the fourth quarter of 2013. ST does have an understanding that Globalfoundries would license the process and provide volume manufacturing.
ARM has been working extensively with leading EDA companies and foundries developing physical design kits, design flows and test chips to prove out both bulk CMOS at 28-nm and 20-nm, and on FinFET designs with TSMC and Globalfoundries at below 20-nm. A similar body of work has not been publicized around the FDSOI process.
"At the moment it is effectively a proprietaty technology. We can help ST if they can proliferate the technology," said East.
East declined to be drawn on whether ARM's own "big-little" technology – where a power-optimized processor core is paired with a performance-optimized core as part of a dynamic voltage and frequency scaling regime – is a good fit with FDSOI. FDSOI can save power but also achieve-leading edge clock frequency through an extended operation voltage range.
"Big-little is a technique for achieving power efficiency. FDSOI is another technique. There's room for lots of techniques. Our people have seen the demos. We don't need to amend our IP. The ST demos are based on ARM anyway," said East.
"The physical IP we need to create is essentially the same [as for bulk CMOS]." - this can't be true. Layout and DRC rules are bound to be different. Is there any way to automatically transfer the layout data from bulk CMOS to FD SOI? I doubt it
It is kind of same dilemma like DUV immersion. When down to 14nm, both of them will be out of gas. How come foundry would pump in resources for this temporary solution which extend for 2 generations? Besides, SOI wafer capacity(Soitec)and Technology(ST)would be roadblockers for proliferation.
Thank you Kris for your question about design portability.
28nm FD-SOI technology adopts the same design rules as ISDA 28LP HKMG gate-first process, with minor changes and some incremental addition for the FD-SOI specific constructs (like the rules for the hybridation zone, allowing the integration of bulk "hybrid" devices in the FD-SOI technology).
The PDK include scripts for automatic porting of schematics and layouts, easing the porting job.
Of course, digital libraries will need to be re-extracted and recharacterized, while analog blocks will require to be readjusted/ retuned because of the different electrical performances of FD-SOI technology.
Giorgio Cesana, STMicroelectronics
SOI wafers/substrates are significantly more expensive compared to bulk.
On the other hand SOI requires less capex because the wafers are preimplanted requiring less equipment at fab level.
It's a trade off between fix cost versus variable cost.
If you can improve yields very quickly SOI is promising - if not you're wasting very expensive silicon.
It's a trade off and Bohr said they were looking closely at both ... SOI and bulk...and he also did not exclude that some chipmakers might come out with SOI approach...
BTW I spent lots of time in Agrate (when it was still SGS) as well in Grenoble (Thompson) and of course I love Catania -
hey a fab in Sicily -
who can ask for more.
@resistion & Kresearch - FD-SOI scales to 10nm -- see http://www.eetimes.com/electronics-news/4403224/FDSOI-roadmap-renames-20-nm-node-as-14-nm. @Kresearch - wafer capacity is in place -- see http://www.advancedsubstratenews.com/2012/12/the-transition-to-fully-depleted/. @the_floating_gate re: cost/yield -- see Handel Jones showing *major* savings w/FD-SOI (who btw presented at the Common Platform Technology Forum yesterday) http://www.advancedsubstratenews.com/2012/11/ibs-study-concludes-fd-soi-most-cost-effective-technology-choice-at-28nm-and-20nm/
thank you Giorgio...interesting comments about hybridization zone...would you (or STM in general) be interested to describe FD-SOI technology for the upcoming Semiconductor Devices book I am editing? firstname.lastname@example.org
SOI industry talk has been going on for 20 years without commercial success.
AMD dropping SOI due to high cost, design IP, and no chip level advantage
FD-SOI has the same issues
- high cost issue: (single supplier),
- Physical design IP not compatible (ESD ckts, poor high voltage devices, limited and DRC restrictions on multi threashold devices)
@Mrchipguy -- I'd posit that FD does not in fact have the same issues as PD. re: cost - there are 3 wafer suppliers (Soitec, SEH, MEMC). Also suggest Handel Jones' piece cited in my previous comment (he's got FD-SOI die cost = 50 to 60% savings compared to bulk or FinFET). re: physical design -- for ESD etc, because the top Si and insulating layers are so thin, for those devices they just etch back to the bulk (this is the "hybridization zones") -- you can read a full explanation in a white paper by Giorgio Cesana et al from a year ago at http://www.soiconsortium.org/pdf/fullydepletedsoi/planar_fd_silicon_technology_competitive_soc_28nm.pdf. And what they're doing with biasing is awesome.
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I am really curious about this cost comparision model
I don't believe there is no defined cost saving because you compare variable cost (SoC wafers) versus fixed cost due to additional capex required due to using bulk
I am curious about the assumptions in this model
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