LONDON – Warren East, CEO of processor IP licensor ARM, says the company stands ready to help STMicroelectronics make a success of its fully-depleted silicon-on-insulator (FDSOI) chip manufacturing process, but that it is up to ST to make the process more widely available.
Speaking to EE Times in a discussion of ARM's 4Q12 and full year financial results East said of FDSOI: "We think it is pretty good technology and we would encourage ST to proliferate it. The physical IP we need to create is essentially the same [as for bulk CMOS]."
FDSOI has emerged at the 28-nm node as a potential chip manufacturing alternative to bulk planar CMOS, which is being pushed to 20-nm by foundries such as Taiwan Semiconductor Manufacturing Co. Ltd. and Globalfoundries Inc. Both those foundries then propose to move rapidly to FinFET-based processes at nodes labeled 16-nm and 14-nm, respectively.
Some observers have argued that 20-nm bulk planar CMOS will not produce significant power savings while being hard to manufacture. The FinFET processes, where transistors are created in fins standing proud of the silicon surface, could be even more complicated to make and harder to yield.
However, the FDSOI process developed by STMicroelectronics does not yet have any high volume or foundry manufacturing capacity in place. The earliest that any could come on-stream would be the fourth quarter of 2013. ST does have an understanding that Globalfoundries would license the process and provide volume manufacturing.
ARM has been working extensively with leading EDA companies and foundries developing physical design kits, design flows and test chips to prove out both bulk CMOS at 28-nm and 20-nm, and on FinFET designs with TSMC and Globalfoundries at below 20-nm. A similar body of work has not been publicized around the FDSOI process.
"At the moment it is effectively a proprietaty technology. We can help ST if they can proliferate the technology," said East.
East declined to be drawn on whether ARM's own "big-little" technology – where a power-optimized processor core is paired with a performance-optimized core as part of a dynamic voltage and frequency scaling regime – is a good fit with FDSOI. FDSOI can save power but also achieve-leading edge clock frequency through an extended operation voltage range.
"Big-little is a technique for achieving power efficiency. FDSOI is another technique. There's room for lots of techniques. Our people have seen the demos. We don't need to amend our IP. The ST demos are based on ARM anyway," said East.
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