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GloFo, Samsung in race to 14nm

Race to 14-nm FinFETs
2/6/2013 10:00 AM EST
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resistion
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re: GloFo, Samsung in race to 14nm
resistion   6/12/2013 11:52:33 PM
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All indications are Intel will use multiple patterning without EUV for 10 nm. The other foundries will likely follow.

resistion
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re: GloFo, Samsung in race to 14nm
resistion   6/12/2013 3:57:19 PM
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http://www.theregister.co.uk/2013/05/29/euv_lithography_still_out_there/

resistion
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re: GloFo, Samsung in race to 14nm
resistion   2/12/2013 1:47:24 AM
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DRAM companies already moving on to 2x nm, so they're not waiting for EUV either.

help.fulguy
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re: GloFo, Samsung in race to 14nm
help.fulguy   2/11/2013 11:33:07 PM
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Bunch of losers. Ages behind Intel.

resistion
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re: GloFo, Samsung in race to 14nm
resistion   2/9/2013 2:21:27 PM
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It can't be gate length anymore but it might be fin CD.

Plasmon
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re: GloFo, Samsung in race to 14nm
Plasmon   2/9/2013 12:39:59 PM
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"7nm" is the name of the node, not the CD needed to print. See ITRS roadmap or Wikipedia for details. Thanks

michigan0
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re: GloFo, Samsung in race to 14nm
michigan0   2/8/2013 7:40:17 AM
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Scalability of the planer bulk technology ends at 28nm because world major foundries; TSMC, Samsung, GlobalFoundries, and UMC all get on to Intelís FinFET bandwagon after falling behind Intel. They all plan to introduce FDFinFETs at 14nm node in 2014, skipping the 22nm, at the same time of Intelís 14nm introduction. The foundries schedule looks unrealistic, and planed aggressively not to behind falling too far behind Intel. It leaves IBM being the only major company adopting FDSOI scaled to 10nm. For 22nm FDSOI about 6nm SOI thickness is required to suppress transistor leakage current, while for 22nm FDFinFET the fin width as large as 22nm is required to suppress the transistor leakage current. In my opinion that is the main reason why Intelís 22nm FinFETs are in high volume manufacturing today for more than a year, but 22nm FDSOI is not. For 14nm FDSOI about 4nm SOI is required while for 14nm FinFETs the fin width as large as 14nm is required to suppress transistor leakage currents. Thus, FDFinFETs show large advantages in manufacturability as transistor is scaled. Soitec can deliver today only the 28nm SOI wafers with 12nm SOI and 25nm buried oxide. Skim

Diogenes53
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re: GloFo, Samsung in race to 14nm
Diogenes53   2/8/2013 3:46:36 AM
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Some of us have been saying for years that the pursuit of x-ray lithography, whether hard x-ray (~1nm) or soft x-ray (~13nm), a.k.a. EUV, was a supreme waste of millions of man-hours and billions of dollars. There were source/mask/resist issues 25 years ago, and there are source/mask/resist issues today. The pursuit of shiny penny alternatives continued, each of them with source, mask, and/or resist issues. The latest distraction is direct self-assembly. Good luck with that. Meanwhile, the choice was clear: shut down Moore's Law and its replenishable pot of gold, or extend optical. If optical was to be extended beyond what most folks thought possible, it would be essential to integrate design and manufacturing, which would result is the re-integration of the disaggregated semiconductor industry, and consequently, the ultimate supremacy of the old-fashioned IDM. Wonder if EUV/x-ray will be ready at 500 angstroms? Let's see: how large will the OPC features be. Or is that XPC?

mranderson
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re: GloFo, Samsung in race to 14nm
mranderson   2/8/2013 3:13:46 AM
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I would say that there are several more customers. People are willing to pay for advances in consumer and industrial electronics, but more products will become commodities with only software and firmware to provide differentiation. Many cell phone designs are already starting to look and feel similar to each other. I would not be surprised though to see people sneak in a special 28nm chip for example into their designs for some hardware customization for say a 8 inch or larger tablet form factor device.

resistion
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re: GloFo, Samsung in race to 14nm
resistion   2/8/2013 3:11:49 AM
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Indeed,the benefit of vertical integration from silicon design to product.

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