Meanwhile a race to next-gen node continues. To accelerate progress the Common Platform partners agreed that starting this year technology developed at the group’s Albany, New York, facility will be directly transferred to partners. Previously it went first to IBM’s Yorktown, New York fab, then to partners.
“We just eliminated a step to market,” said IBM’s Patton.
Globalfoundries and Samsung are both running test shuttles this year for 14 nm with FinFETs. Both aim to have their first production wafers out by the end of the year if all goes well.
Globalfoundries reported more than 60 percent improvements in power or performance at 14 nm compared to 28 nm, based on a test chip using a dual-core ARM Cortex A9. In addition, it is working with Synopsys on an EDA flow and with Rambus on migrating 28 nm IP to the new node.
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Globalfoundries says a dual-core A9 test chip showed 14 nm gives 60%+ boost over 28 nm.
K.H. Kim, executive vice president of Samsung's foundry business, said the company will run 14 nm test shuttles for select customers in April and September. It has 14 nm IP partnerships with ARM, Synopsys and Analog Bits.
Meanwhile, Samsung is converting its Austin, Texas fab from memory to logic, expecting the first 28 nm wafers from it this year. It also will produce 20 and 14 nm wafers starting as early as the end of 2014 in a new fab in Korea.
“We will have enough capacity to serve you,” Kim told attendees in a keynote.
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Samsung readies two 14 nm shuttles this year with hopes for production wafers before January.
It’s not clear how much chip designers will demand the 14 nm FinFET process which carries significant costs and marginal advantages over a coming 20 nm node.
The 20 nm node is the first to require double patterning, a cost adder. The 14 nm node is essentially a 20 nm process with FinFETs, another cost, said IBM’s Patton.
“It’s not a true shrink, but when you get to 10 nm it is a true shrink and I expect significant cost benefits,” Patton said. “Is there still a cost benefit [with 14 nm]? Absolutely, it just won’t be as large as it was historically,” he added.
“We believe 28 nm will be a very long node, a very cost competitive solution,” said Kim.
Market watcher Handel Jones of International Business Strategies (Los Gatos, Calif.) said FinFETs present real challenges for mixed-signal designs, potentially delaying the node’s ramp.
Nevertheless, he said Globalfoundries and Samsung have a significant opportunity to grab market share from TSMC. In addition, IBM’s Burlington fab is doing “extremely well” in RF, he added.
Scalability of the planer bulk technology ends at 28nm because world major foundries; TSMC, Samsung, GlobalFoundries, and UMC all get on to Intel’s FinFET bandwagon after falling behind Intel. They all plan to introduce FDFinFETs at 14nm node in 2014, skipping the 22nm, at the same time of Intel’s 14nm introduction. The foundries schedule looks unrealistic, and planed aggressively not to behind falling too far behind Intel. It leaves IBM being the only major company adopting FDSOI scaled to 10nm. For 22nm FDSOI about 6nm SOI thickness is required to suppress transistor leakage current, while for 22nm FDFinFET the fin width as large as 22nm is required to suppress the transistor leakage current. In my opinion that is the main reason why Intel’s 22nm FinFETs are in high volume manufacturing today for more than a year, but 22nm FDSOI is not. For 14nm FDSOI about 4nm SOI is required while for 14nm FinFETs the fin width as large as 14nm is required to suppress transistor leakage currents. Thus, FDFinFETs show large advantages in manufacturability as transistor is scaled. Soitec can deliver today only the 28nm SOI wafers with 12nm SOI and 25nm buried oxide. Skim
Some of us have been saying for years that the pursuit of x-ray lithography, whether hard x-ray (~1nm) or soft x-ray (~13nm), a.k.a. EUV, was a supreme waste of millions of man-hours and billions of dollars. There were source/mask/resist issues 25 years ago, and there are source/mask/resist issues today. The pursuit of shiny penny alternatives continued, each of them with source, mask, and/or resist issues. The latest distraction is direct self-assembly. Good luck with that. Meanwhile, the choice was clear: shut down Moore's Law and its replenishable pot of gold, or extend optical. If optical was to be extended beyond what most folks thought possible, it would be essential to integrate design and manufacturing, which would result is the re-integration of the disaggregated semiconductor industry, and consequently, the ultimate supremacy of the old-fashioned IDM. Wonder if EUV/x-ray will be ready at 500 angstroms? Let's see: how large will the OPC features be. Or is that XPC?
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.