SANTA CLARA, Calif. – Globalfoundries and Samsung are in a dead heat to get their first 14 nm production wafers out before the end of the year, aiming to beat rival Taiwan Semiconductor Manufacturing Co. by as much as a year. Meanwhile, an IBM building in New York sits empty, waiting for an extreme ultraviolet (EUV) lithography machine to light the way to the industry’s longer-term future.
That was the picture from the annual event here of the trio’s Common Platform alliance.
The companies said they now expect EUV will not be ready until the 7-nm node. It remains their primary bet on the future of chip making, but it will require advances in physics on several fronts to succeed, said a top IBM technologist.
“We’re in the most complex business in the history of human kind,” said Mike Noonen, vice president and marketing at sales at Globalfoundries.
Mike Cadigan, head of IBM’s semiconductor group, told New York state officials he needed before the end of 2012 a new building to house the latest EUV prototype tool. Now the building is complete, but the tool may not arrive until April or later.
“The industry voted [with investments in 2012] that we need to make this work, but there continues to be a lot of unknowns,” Cadigan told press. “You can continue to view EUV as next to impossible, but the industry needs it,” he said.
Developers improved the strength of EUV’s laser light tenfold to 30W, but they still need to improve it another tenfold to 250W before it is ready, said Gary Patton, a chief technologist in IBM’s chip group.
In addition, engineers need to eliminate problems in resists, mask defects and inspection processes. Patton compared that to searching for golf balls in an area as large as one tenth of the state of California.
Click on image to enlarge.
IBM detailed physics challenges ahead for EUV.
“You actually drop molten tin at 150 mph, zap it with a laser, blast it with a CO2 laser to generate plasma, eliminate the debris from that, collect the light, purify and then bounce it back and forth off six mirrors,” he said. “These are real physics problems we have to solve,” he added.
Patton described several advances in double patterning that aim to at least reduce the need for triple or quad patterning with today’s immersion lithography at 14 and 10 nm nodes. Those tools could also be used at the 7-nm node if needed, he said.
Cadigan and Noonen suggested the fully depleted silicon-on-insulator technology promoted by STMicroelectronics could form another alternative. Globalfoundries aims to have volume production of FD-SOI before June 2014, Noonen said.
EUV also gates the move to 450 mm wafers, now expected about 2020, said IBM’s Cadigan. “With immersion you are challenged on the return on investment in 450 mm,” he said.
So industry is already thinking about 7nm ? How far we can shrink the transistor ? I think we are approaching the limit and soon companies will start building new architecture's to enhance the performance instead of worry about shrinking the transistor.
I am wondering if Samsung/Gloflo "roadmap" was backed up by a manufacturing/litho roadmap.
I clicked on the slides - one said 14nm on track...
I would imagine being a customer you would want to now what process you actually use before taping it out?
ASML mentioned that foundry process would require EUV @14nm - I am curious why TSMC selected 16nm FinFet as next generation following 20nm planar.
"It’s not clear how much chip designers will demand the 14 nm FinFET process which carries significant costs and marginal advantages over a coming 20 nm node."
Shouldn't they figure this out?
I get impression they just follow blindly Intel roadmap.
The 20 nm node is the first to require double patterning, a cost adder. The 14 nm node is essentially a 20 nm process with FinFETs, another cost, said IBM’s Patton.
That comes from an "IBMer" - makes me scratch my head -
imagine you are a potential customer and you evaluate TSMC, Gloflo and Samsung.
which one would you pick?
Fully depleted technologies like FDSOI and FinFET use undoped channels- so basically zero dopants, except for the source and drain. Of course there may be some doping of Fins for various reasons in the early implementations, but ultimately it will be undoped channels. And junctionless transistors have been demonstrated as well if you are worried about the S/D doping.
Oh and P.S. "everyone thought" 100nm was the limit at one time as well. I have yet to hear Intel, IBM, Samsung, TSMC or any IDM/Foundry say there is any hard limit in the foreseeable future. The limit will come from economics, not physics- it will just get too expensive to stay on Moore's law at some point.
Surprised the article didn't mention DSA prominently (directed self assembly)- they spent some time on that as well and that can reduce the need for double/triple/quadruple patterning as well. That is one area where IBM has made some real advances. But I don't recall seeing any litho roadmap slide- no.
And to their credit (contrary to your impression) they don't seem to be following blindly the Intel roadmap. K. Kuhn and M. Bohr have been touting tunnel FETs and Ge/III-V channels lately. IBM basically dismissed those solutions and said Si nanowire followed by carbon nanotubes is how they think it will go.
This would explain why TSMC sticks with 16nm rather 14nm.
I believe back in July during ASML CC ASML stated that foundries face additional challenge compared to IDM due to design rules / (aggressive) shrinkfactor and the conclusion from what I recall was that foundries would need EUV @14nm.
I believe they also stated that DRAM people would be first in adopting EUV.