SANTA CLARA, Calif. – Globalfoundries and Samsung are in a dead heat to get their first 14 nm production wafers out before the end of the year, aiming to beat rival Taiwan Semiconductor Manufacturing Co. by as much as a year. Meanwhile, an IBM building in New York sits empty, waiting for an extreme ultraviolet (EUV) lithography machine to light the way to the industry’s longer-term future.
That was the picture from the annual event here of the trio’s Common Platform alliance.
The companies said they now expect EUV will not be ready until the 7-nm node. It remains their primary bet on the future of chip making, but it will require advances in physics on several fronts to succeed, said a top IBM technologist.
“We’re in the most complex business in the history of human kind,” said Mike Noonen, vice president and marketing at sales at Globalfoundries.
Mike Cadigan, head of IBM’s semiconductor group, told New York state officials he needed before the end of 2012 a new building to house the latest EUV prototype tool. Now the building is complete, but the tool may not arrive until April or later.
“The industry voted [with investments in 2012] that we need to make this work, but there continues to be a lot of unknowns,” Cadigan told press. “You can continue to view EUV as next to impossible, but the industry needs it,” he said.
Developers improved the strength of EUV’s laser light tenfold to 30W, but they still need to improve it another tenfold to 250W before it is ready, said Gary Patton, a chief technologist in IBM’s chip group.
In addition, engineers need to eliminate problems in resists, mask defects and inspection processes. Patton compared that to searching for golf balls in an area as large as one tenth of the state of California.
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IBM detailed physics challenges ahead for EUV.
“You actually drop molten tin at 150 mph, zap it with a laser, blast it with a CO2 laser to generate plasma, eliminate the debris from that, collect the light, purify and then bounce it back and forth off six mirrors,” he said. “These are real physics problems we have to solve,” he added.
Patton described several advances in double patterning that aim to at least reduce the need for triple or quad patterning with today’s immersion lithography at 14 and 10 nm nodes. Those tools could also be used at the 7-nm node if needed, he said.
Cadigan and Noonen suggested the fully depleted silicon-on-insulator technology promoted by STMicroelectronics could form another alternative. Globalfoundries aims to have volume production of FD-SOI before June 2014, Noonen said.
EUV also gates the move to 450 mm wafers, now expected about 2020, said IBM’s Cadigan. “With immersion you are challenged on the return on investment in 450 mm,” he said.
So industry is already thinking about 7nm ? How far we can shrink the transistor ? I think we are approaching the limit and soon companies will start building new architecture's to enhance the performance instead of worry about shrinking the transistor.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.