SAN FRANCISCO – Yongmin Shin stood at the lectern facing a long line of his competitors queued up at the microphone. It was a moment of truth—and obfuscation.
He had just described some of the inner workings of Samsung’s latest mobile applications processor in one of the most anticipated talks at the International Solid State Circuits Conference. Now engineers from Apple, Qualcomm, Intel and other rivals were ready to lob questions at him.
First to the mic was an engineer from Apple, one of Samsung’s largest customers and biggest rivals. The two companies pounded each other over patent infringement in a San Jose courtroom just six months earlier.
The Apple engineer wanted to know details about the method Shin sketched out turning down the dial on the power supply to the chip as it decreases in data rate (below). “It depends on case by case” circumstances, said Shin deflecting the question, and sparking a few chuckles in the audience.
Click on image to enlarge.
Samsung steps down the clock on Exynos--but won't say exactly how.
An Analog Devices engineer went next, digging deeper."Does it really make sense to burn up to six times the power in an array of ARM Cortex A15 cores for just twice the performance of an array of A7s?," he asked.
“That’s a good question,” Shin responded. “Sometimes we have to use high power dissipation because we have to hit the performance target of the application,” he said defending the ARM big.little approach of the Samsung chip he described.
How do you know when to switch between the big bank of A15s and the little bank of A7s, asked the ADI engineer in a counter-punch.
“I am just a circuit engineer, not the software guy--they can explain about this,” he said, again deflecting the question and getting a laugh from the audience.
Next an Intel engineer wanted to know the latency when switching between the two CPU banks. “This is a circuit conference not a software conference, I cannot answer that,” Shin said, setting off another wave of laughs.
Read Anand's article about the Exynos Octa: http://www.anandtech.com/show/6768/samsung-details-exynos-5-octa-architecture-power-at-isscc-13
Around 5W max power for quad 1.8GHz A15 cores is actually amazingly low. That's just 1.25W per core.
If anything, the large difference in power between A7 and A15 means that big.LITTLE has achieved its goal. Most of the time you will be running on the A7 cores, thus using only a fraction of the power (about 0.5W for 4 1.2GHz A7 cores according to the graph).
I remember this presentation. I was there. Yongmin also talked about body biasing both forward and reverse to boost performance and reduce leakage respectively. So I got to the mic and asked him if they applied body biasing on both pmos and nmos devices or only one of them. He refused to answer. I asked him if he could at least shed some light on how much leakage decrease or what performance boost he got. Again, he refused to answer. Mr Shin was right on one point this is a circuits conference. A conference which is place where you come to share your technologies and ideas and help advance the field. This paper should not have been selected. You cannot mention you tried various power saving schemes without a mention of what the benefit was. The presentation seemed more like a press release rather than a conference presentation. ISSCC should send a clear message. If you want to present here - you have to share information. You cannot use it as a platform to only advertize your wares.
In Mr. Shin's defense, he was probably forced to not reveal anything.
A great question. And I must say, when I attend ISSCC and other such conferences, I am always struck with how much technical detail engineers are willing/able to share with a room fully of other engineers, some of whom happen to work for their fiercest rivals. It's got to be a delicate balance. I must also say that I too have observed presentations by Samsung where the presenter did not appear to want to answer detailed questions. Not faulting Samsung for this, but perhaps it is part of that particular company's policy.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.