Breaking News
News & Analysis

Slideshow: Samsung cagey on smartphone SoC at ISSCC

2/27/2013 08:00 PM EST
8 comments
NO RATINGS
Page 1 / 5 Next >
More Related Links
View Comments: Newest First | Oldest First | Threaded View
KRS03
User Rank
Rookie
re: Slideshow: Samsung cagey on smartphone SoC at ISSCC
KRS03   3/7/2013 12:29:57 AM
NO RATINGS
Yes, But just imagine the 10x draw on the battery to keep the 5x quad going. Battery weight is the driver here.

Hughston
User Rank
CEO
re: Slideshow: Samsung cagey on smartphone SoC at ISSCC
Hughston   3/5/2013 3:32:13 PM
NO RATINGS
It's not a failure of ARM but a failure of poor system architectures.

AliNS
User Rank
Rookie
re: Slideshow: Samsung cagey on smartphone SoC at ISSCC
AliNS   3/1/2013 6:34:12 PM
NO RATINGS
Wow! In this case, it's a big price to pay to have a 5x larger quad-core processor idling by while using the low power core.

Wilco1
User Rank
CEO
re: Slideshow: Samsung cagey on smartphone SoC at ISSCC
Wilco1   3/1/2013 2:13:39 PM
NO RATINGS
Read Anand's article about the Exynos Octa: http://www.anandtech.com/show/6768/samsung-details-exynos-5-octa-architecture-power-at-isscc-13 Around 5W max power for quad 1.8GHz A15 cores is actually amazingly low. That's just 1.25W per core. If anything, the large difference in power between A7 and A15 means that big.LITTLE has achieved its goal. Most of the time you will be running on the A7 cores, thus using only a fraction of the power (about 0.5W for 4 1.2GHz A7 cores according to the graph).

help.fulguy
User Rank
Manager
re: Slideshow: Samsung cagey on smartphone SoC at ISSCC
help.fulguy   2/28/2013 8:46:56 PM
NO RATINGS
big.Little is nothing but a big failure of ARM. The power is going thru the roof to get minor performance gain. ARM has lost the power battle to Intel.

NikhilJK
User Rank
Rookie
re: Slideshow: Samsung cagey on smartphone SoC at ISSCC
NikhilJK   2/28/2013 7:38:07 PM
NO RATINGS
I remember this presentation. I was there. Yongmin also talked about body biasing both forward and reverse to boost performance and reduce leakage respectively. So I got to the mic and asked him if they applied body biasing on both pmos and nmos devices or only one of them. He refused to answer. I asked him if he could at least shed some light on how much leakage decrease or what performance boost he got. Again, he refused to answer. Mr Shin was right on one point this is a circuits conference. A conference which is place where you come to share your technologies and ideas and help advance the field. This paper should not have been selected. You cannot mention you tried various power saving schemes without a mention of what the benefit was. The presentation seemed more like a press release rather than a conference presentation. ISSCC should send a clear message. If you want to present here - you have to share information. You cannot use it as a platform to only advertize your wares. In Mr. Shin's defense, he was probably forced to not reveal anything.

mcgrathdylan
User Rank
Blogger
re: Slideshow: Samsung cagey on smartphone SoC at ISSCC
mcgrathdylan   2/28/2013 5:18:29 PM
NO RATINGS
A great question. And I must say, when I attend ISSCC and other such conferences, I am always struck with how much technical detail engineers are willing/able to share with a room fully of other engineers, some of whom happen to work for their fiercest rivals. It's got to be a delicate balance. I must also say that I too have observed presentations by Samsung where the presenter did not appear to want to answer detailed questions. Not faulting Samsung for this, but perhaps it is part of that particular company's policy.

rick merritt
User Rank
Author
re: Slideshow: Samsung cagey on smartphone SoC at ISSCC
rick merritt   2/28/2013 3:29:55 PM
NO RATINGS
What do we share, what do we keep hidden when it comes to our biggest projects and hottest markets?

Most Recent Comments
August Cartoon Caption Winner!
August Cartoon Caption Winner!
"All the King's horses and all the KIng's men gave up on Humpty, so they handed the problem off to Engineering."
5 comments
Top Comments of the Week
Like Us on Facebook

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
EE Times on Twitter
EE Times Twitter Feed
Flash Poll
Radio
LATEST ARCHIVED BROADCAST
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.