In EDA, Synopsys “Yield Explorer is a great tool, but it still looks planar--it needs to evolve into a 3-D tool,” he said. “Tools from Synopsys and others are woefully lacking in compressing a simple ATE pattern that can step backwards to find faults,” he added.
Jain and Campbell both expect to see some of the first 14 nm FinFET chips hit the market in late 2014 if the current issues get addressed.
“I would say the processes are close to being ready but the design flows still need work,” said Campbell. “Today we build [14 nm FinFET] test chips with 20 million gates, but a commercial SoC may have is two billion gates,” he said giving one measure of the work ahead.
Joachim Kunkel, general manager of Synopsys’ IP core group, provided another snapshot of the progress to date.
His group taped out a 20 nm test chip in April 2012 that showed working MIPI, PCI Express and USB interfaces using double patterning. A follow up 14 nm chip was a simpler device mainly focused on memory, and has not yet come back from the fab.
“The design parameters for FinFETs are very different from those of the planar nodes,” Kunkel said.
"The differences between the various FinFET processes available from the foundries today are significant enough that we have to start over [with IP development] each time," he said. "Also, most FinFET processes and design kits are still in the development phase, adding to the effort," he added.
FinFETs “will drive a complete re-evaluation of your architecture--how you separate out devices and optimize them—it’s a big change,” Campbell said.
Nevertheless, “the whole industry is trying to pull in the first generation of FinFETs in terms of time to volume,” said Subramani Kengeri, vice president of design solutions at Globalfoundries.
In the race to catch up with Intel’s 22 nm FinFET process, now in production, foundries have agreed to take two separate steps, he said. First they are tackling at 20 nm the need for double patterning with 193-nm lithography. Then they are adding 14 nm FinFETs as “front end” devices in a node that still uses 20 nm “back end” interconnects, he said.
Kyu-Myung Choi, senior vice president of Samsung’s infrastructure design center for logic, reiterated the Korean giant’s promise to have a 14 nm FinFET process ready for “risk production” by the end of 2013. Both Choi and Kengeri said work on the 14 nm node is on track in terms of yields and performance.
Intel's FinFETs approach draws fire from rivals
Intel's FinFETs are less fin and more triangle
TSMC taps ARM's V8 on road to 16-nm FinFET
Slideshow: IBM outlines fab future beyond FinFETs