SANTA CLARA, Calif. – FinFETs hold both promise and peril and are not yet ready for prime time, according to a panel of experts who spoke on their experiences with the technology at the annual Synopsys User Group meeting here.
The 3-D transistor structures coming at the 14-nm node promise either performance increases or power consumption reductions of more than 60 percent compared to today’s 28 nm process, according to a Globalfoundries technical executive. However, they increase gate capacitance on a per micron basis, raising a handful of old and new design issues, said others on the panel.
FinFETs bring a 66 percent increase in gate capacitance per micron compared to today’s-28 nm process, back up to the level of the 130-nm planar node, said Anil Jain, vice president of IC engineering at Cavium Networks. Capacitance will limit both performance increases and dynamic power scaling for high-end chips, he said.
“We have these beautiful [3-D] transistors, but we can’t run them too far,” Jain said, noting “dynamic power [is] getting out of hand.” In addition, “those of us in high performance devices have not seen much improvement in core voltage scaling,” he said.
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Cavium estimates a 40 percent increase in gate capacitance due to FinFETs.
Jain asked EDA vendors for tools that do a better job controlling switching power and isolating electro-migration faults. “FinFETs are not a no-brainer migration--at the end of the day we have to pay for it, so please don’t blow up our costs,” he added.
Michael Campbell, a vice president of engineering in Qualcomm’s chip design group, said FinFET structures in one foundry are “similar, but not the same” as those in another foundry. “You can only etch in certain directions and etch tools are common—that drives some similarities--but [foundries] use different in tricks in spatial walls and diffusion,” he said.
Campbell noted pictures of Intel’s 22 nm FinFETs show irregularly tapered walls that could impact planar fault models. “It takes new test technologies and incredibly deep partnerships to do design for test properly,” he said.