SANTA CLARA, Calif. – FinFETs hold both promise and peril and are not yet ready for prime time, according to a panel of experts who spoke on their experiences with the technology at the annual Synopsys User Group meeting here.
The 3-D transistor structures coming at the 14-nm node promise either performance increases or power consumption reductions of more than 60 percent compared to today’s 28 nm process, according to a Globalfoundries technical executive. However, they increase gate capacitance on a per micron basis, raising a handful of old and new design issues, said others on the panel.
FinFETs bring a 66 percent increase in gate capacitance per micron compared to today’s-28 nm process, back up to the level of the 130-nm planar node, said Anil Jain, vice president of IC engineering at Cavium Networks. Capacitance will limit both performance increases and dynamic power scaling for high-end chips, he said.
“We have these beautiful [3-D] transistors, but we can’t run them too far,” Jain said, noting “dynamic power [is] getting out of hand.” In addition, “those of us in high performance devices have not seen much improvement in core voltage scaling,” he said.
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Cavium estimates a 40 percent increase in gate capacitance due to FinFETs.
Jain asked EDA vendors for tools that do a better job controlling switching power and isolating electro-migration faults. “FinFETs are not a no-brainer migration--at the end of the day we have to pay for it, so please don’t blow up our costs,” he added.
Michael Campbell, a vice president of engineering in Qualcomm’s chip design group, said FinFET structures in one foundry are “similar, but not the same” as those in another foundry. “You can only etch in certain directions and etch tools are common—that drives some similarities--but [foundries] use different in tricks in spatial walls and diffusion,” he said.
Campbell noted pictures of Intel’s 22 nm FinFETs show irregularly tapered walls that could impact planar fault models. “It takes new test technologies and incredibly deep partnerships to do design for test properly,” he said. Targeting chips in late 2014 In EDA, Synopsys “Yield Explorer is a great tool, but it still looks planar--it needs to evolve into a 3-D tool,” he said. “Tools from Synopsys and others are woefully lacking in compressing a simple ATE pattern that can step backwards to find faults,” he added.
Jain and Campbell both expect to see some of the first 14 nm FinFET chips hit the market in late 2014 if the current issues get addressed.
“I would say the processes are close to being ready but the design flows still need work,” said Campbell. “Today we build [14 nm FinFET] test chips with 20 million gates, but a commercial SoC may have is two billion gates,” he said giving one measure of the work ahead.
Joachim Kunkel, general manager of Synopsys’ IP core group, provided another snapshot of the progress to date.
His group taped out a 20 nm test chip in April 2012 that showed working MIPI, PCI Express and USB interfaces using double patterning. A follow up 14 nm chip was a simpler device mainly focused on memory, and has not yet come back from the fab.
“The design parameters for FinFETs are very different from those of the planar nodes,” Kunkel said.
"The differences between the various FinFET processes available from the foundries today are significant enough that we have to start over [with IP development] each time," he said. "Also, most FinFET processes and design kits are still in the development phase, adding to the effort," he added.
FinFETs “will drive a complete re-evaluation of your architecture--how you separate out devices and optimize them—it’s a big change,” Campbell said.
Nevertheless, “the whole industry is trying to pull in the first generation of FinFETs in terms of time to volume,” said Subramani Kengeri, vice president of design solutions at Globalfoundries.
In the race to catch up with Intel’s 22 nm FinFET process, now in production, foundries have agreed to take two separate steps, he said. First they are tackling at 20 nm the need for double patterning with 193-nm lithography. Then they are adding 14 nm FinFETs as “front end” devices in a node that still uses 20 nm “back end” interconnects, he said.
Kyu-Myung Choi, senior vice president of Samsung’s infrastructure design center for logic, reiterated the Korean giant’s promise to have a 14 nm FinFET process ready for “risk production” by the end of 2013. Both Choi and Kengeri said work on the 14 nm node is on track in terms of yields and performance.
40% or 66 % higher capacitance "equal to 130nm "and little supple voltage scaling !
Thus Power can not be lower based on physics Power being proportional to C and V*V . I am loosing all respect for TSMC and GF marketing.
Rick or anyone else any comment?
Valid concerns with the increased capacitance, however that only points out a potential increase in dynamic power. Recently, leakage power has been of major concern in Deep Submicron Planar technologies. This power is consumed while the gates are not switching and historically have contributed much of the power. Perhaps finfets offer the benefit of reduced leakage power.....
I guess I should add intel BS marketing as well.
Paul O. CEO has been talking about a finfet and winning mobile for past 3 years. yet intel still not shipping mobile atoms using finfet. In fact Paul will be pushed out of intel before a singe cell phone or table chip ship with finfet ships.
I hear uncompetitive 22nm finfet atoms too high power and shipping slipping to 2014 . I think Rick you found the problem. Capacitance is too high and finfets increase not lower power .
Anil Jain said “ FinFETs bring a 66 percent increase in gate capacitance per micron compared to today’s-28nm process, back up to the level of the 130-nm planar node”. I disagree. At the device level the transistor drive current is improved by high gate capacitance resulted from higher permittivity of the high-k dielectric. However, performance at high operating clock frequency can be negatively impacted by the increased gate capacitance. To minimize this penalty Intel uses the unique HK/MG (high K such as HfO2)/Metal electrode that give intrinsically superior electrostatic control or short channel effect and reduced stand-by power reducing gate current. Therefore, Intel’s HK/MG will provide high performance through higher gate capacitance and concurrently scale down the gate length of the transistor. That is why Intel’s 22nm FinFETs are in high volume manufacturing over a year, and the 14nm FinFETs will be manufactured in 2014. Recently, major foundries, TSMC, Samsung, and others announced to adopt FinFET technology at 14nm and manufacture in 2014, skipping the 22nm to catch up with Intel. However, the successful implementation of FinFET technology will be much easier at the 22nm than at the 14nm node because of the lack of process and manufacturing learning at the 22nm node, resulting in further behind Intel.
The "gate capacitance" is no longer just the inversion gate capacitance. In fact, inversion gate capacitance is just a small portion of the total transistor capacitance. FinFET has significantly higher parasitic capacitance than planar devices, and that's just one of the few reasons even Intel FinFET did not the 50% reduction of active power that was originally claimed.