LAKE TAHOE, Nev.--Achieving the 14-nanometer process technology node will be more difficult than originally imagined, according to experts speaking at the International Symposium on Physical Systems (ISPD), where next-generation semiconductor designers worldwide gather annually.
Semiconductor scaling used to result in both smaller and faster chips, since clock speed and supply voltage used to be directly- and inversely-proportional to device sizes, respectively.
Unfortunately, for the last few generations of process technology, clock speed and supply voltage have changed very little, due to circuit and physical design constraints caused by atomic-scale problems, such as transistor leakage caused by ultra-thin gate oxides. Many stop-gap measures have been adopted, such as thicker high-k dielectrics. But these have only served to delay addressing the root problems until the 14-nanometer node, according to IBM distinguished engineer, James Warnock, in his paper "Circuit and Physical-Design Challenges at the 14-nm Technology Node."
"The 14-nm node poses a host of challenges for designers, because the solutions to problems with scaling have been postponed by previous generations," said Warnock. "The end is nearish, and will eventually be determined by economic issues, but at 14-nm there is no way to get more performance by scaling alone."
The biggest problem with scaling, according to Warnock, has been increased transistor leakage, which designers at previous nodes have mitigated by using steeper sub-threshold slopes and, more recently, by going to high-k dielectrics. In lithography, the lack of commercial extreme ultraviolet (EUV) has been mitigated by double patterning. However, at 14-nm neither of these stop-gaps will work, according to Warnock.
Multi-gate 3-D FinFETs will be an essential element in achieving the 14 nanometer process technology node, according to IBM research scientist James Warnock.
"To solve the leakage problem, multi-gate 3-D FinFETs have already appeared at 22-nm [by Intel] and are quickly being adopted by other chip makers," said Warnock. "FinFETS have inherently steeper threshold slopes and improve random dopant fluctuations [RDFs], but they introduce new sources of variability too--such as fin width and height."
Clearly the dimension scaling is getting more and more challenging, for less and less benefits. Accordingly there are less and and less vendors who still doing it, it is clearly the time to consider other options - of which monolithic 3D IC would be a most compelling one
Of course 14 nm node will be difficult to achieve. But it will be one more way for semiconductor industry "leaders" to differentiate themselves from their competitors. And it will likely drive yet more consolidation in the industry.
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