The 3-D aspect ratio of
FinFETs compounds other problems, such as line-edge roughening and
parasitic capacitance, but also introduces completely new problems. For
instance, FinFETs can only have an integer number of 3-D fins,
presenting designers with choices they have not had to face before, such
as how many fins to use.
One solution is the sea-of-fins
approach whereby the whole surface of a transistor is studded with
dozens of fins, many of which are removed using an etch step. However,
new design tools reflecting the new constraints will be needed to aid
engineers in picking the number and spacing of fins in multi-gate
New lithographic constraints, such as the need for
multi-patterning in 3-D, will also require new tools that permit the
co-design of FinFET architectures that are compatible with standard
libraries. Higher RC delays will also put painful pressures onto
automatic routers to identify and optimize wire planes and vias which
will not scale to 14nm. New tools will also need to mitigate
electro-migration problems as current densities rise in "hot" wires in
order to assure that chip lifetimes are not adversely affected at 14nm.
presenters in the Design for Manufacturability at Advanced Nodes track
included Toshiba scientist Shigeki Nojima who detailed the issues with
optical multi-patterning. University of Tokyo scientist Rimon Ikeno
presented electron-beam tricks-and-tips for advanced nodes, and National
Taiwan University scientist Chung-Wei Lin proposed a structured routing
architecture using superposition for character projection that
restricts via placement and wire-track interchange to reduce layout
patterns at advanced nodes.
Of course 14 nm node will be difficult to achieve. But it will be one more way for semiconductor industry "leaders" to differentiate themselves from their competitors. And it will likely drive yet more consolidation in the industry.
Clearly the dimension scaling is getting more and more challenging, for less and less benefits. Accordingly there are less and and less vendors who still doing it, it is clearly the time to consider other options - of which monolithic 3D IC would be a most compelling one
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.