SAN JOSE, Calif. – Plans to make 3-D chip stacks for next generation smartphones have been pushed out to 2015 or later. But new chip designs for tablets have emerged using simpler 2.5-D stacking techniques that could ship late next year.
The good and bad news comes as Globalfoundries announced its first functional wafers with through silicon vias (TSVs) using the 20-nm process at its Fab 8 in New York. TSVs form the connections between chips in a 3-D stack, and Globalfoundries hopes to be an early implementer of the technology.
A year ago, Globalfoundries announced it was installing equipment at Fab 8 worth “tens of millions” in hopes of shipping 28- and 20-nm 3-D chip stacks in 2014. Now it says it only expects to use the 20-nm process for 3-D chips that may not ship in volume until 2015 or later.
However, the foundry does appear to be accelerating work in 65-nm at its Singpore Fab 7 on 2.5-D stacks that put chips side-by-side on a silicon interposer for a range of uses.
Click on image to enlarge.
Globalfoundries sees three uses cases for 2.5-D stacks and just one for 3-D using TSVs.
The 28-nm work got a double whammy in recent months when both Texas Instruments and STMicroelectronics quietly cancelled projects for chip stacks using a first-generation Wide IO memory from Jedec, running at 12.8 Gbits/second.
Other mobile SoC makers are said to be adopting Jedec’s next-generation WideIO spec that will support data rates up to 25.6 Gbits/s and is expected to be finished by the end of the year. They are targeting the 20-nm node, in which Globalfoundries conducted its latest tests.
TI got out of the smartphone market
I'm less sure about the ST/ST-Ericsson move but assume it was about that company's financial woes more than anything else.
Meanwhile apparently most of the big SoC makers have decided they don't want 28 nm WideIO 1.0 memory at 12G but 20nm WideIO 2.0 at 24G.
"rise above Moore's law"? I think not. the issue here is that numerous segments need 2.5d today, primarily because no one can afford the power and pins to drive enough memory. since this is a power-based argument, actual 3d stacking is mostly irrelevant: the need is many/wide pins from cpu to memory, and no cpu (except perhaps in a phone) can afford to be stacked, dissipation-wise.
memory-wall, meet interposer. that's what's on the table. it's not a fab issue either - denser single chips don't eliminate the need for 2.5d integration - if anything, it gets worse.
a refreshingly honest report on the status of 3-D stacking / 2.5 D modules that exposes the reality of this overly mechanical attempt to rise above Moore's Law or circumvent a bank balance too lean to afford a 14 nm Fab.
Though the partisans of 3-D stacking have for quite a few years now been drooling about the bonanza of the billion units a year Smart Phone industry adopting their technology "any time now", given the laws of physics & economics thats probably one of the last application that would ever happen. Per historical precedence the normal order of adoption for this complex process would be : military, medical, supercomputers, servers, graphics-heavy consumer systems like game systems and perhaps only then Tablets and Smart phones.
And even after all the hardware mfg. issues of 3-d stacks are solved, the architecture and programing issues of hooking up the right chunk of memory to a specific processor core in zillion - core processors would remain just as much a challenge as in any other parallel computer.
2.5 - d modules with Si interposers would provide good enough interconnect density and thus significant improvement in Bandwidth / Power eff. but these Interposers need to be much cheaper than just by 50 % ( Glo Fo target ? ) to prevent the time - tested strategy to integrate the whole shebang on a single chip.
Regarding 2.5-d modules with cheaper organic substrates, the improvement in bandwidth will be severely restricted by interconnect density possible even at future geometries ( 8 um L&S, 30 um dia via ) or no. of layers ( cost ). RC delay and signal skew in resulting long lines between chips would be significant. So not much of a improvement in Bandwidth or power efficiency there.
Elegant electrical methods to work around architectural and physical limits of package level integration are in development and would very likely precede the complex TSV based 2.5 or 3-D processes.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.