Globalfoundries is using a 32 x 26 mm test vehicle in its 65-nm Fab 7 for 2.5-D stacks on silicon interposers. “Our Singapore fab is driving cost down significantly,” said McCann, adding costs still need to drop about 50 percent to enable high volume products.
Many of the apps require High Bandwidth Memory (HBM), another Jedec interface that is still in development. The HBM die will be paired with graphics processors or CPUs increase memory throughput and thus performance. McCann estimates first 2.5-D stacks using HBM could ship in low volumes in 2014.
In addition, Globalfoundries is working with one partner on a lower cost, lower bandwidth option using laminates instead of a silicon interposer. Nvidia also expressed interest in this approach recently.
Separately, Globalfoundries linked two functioning wafers using tens of thousands of TSVs in its New York fab. It gathered electrical verification data on the designs that used copper TSVs at 40- and 20-micron pitch.
McCann expressed optimism about the size of the TSVs and use of copper. In addition, so-called “keep out zones” around the TSVs “turned into a non issue for us,” he said.
“We started at five micron keep-out zones and then went down to 1-2 microns without seeing much impact on digital circuits,” he said. “We don’t need TSVs anywhere near analog circuits today, so we are keeping them away, but we will need to address them for future heterogeneous chips,” he added.
In its tests, the foundry only did limited modeling of thermal issues, expected to be a major challenge when packing processors next to memory. “Mostly that’s work being handled by our customers,” McCann said.
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Globalfoundries used 40 and 20 micron pitch TSVs in its wafer-level electrical tests.