Globalfoundries is using a 32 x 26 mm test vehicle in its 65-nm Fab 7 for 2.5-D stacks on silicon interposers. “Our Singapore fab is driving cost down significantly,” said McCann, adding costs still need to drop about 50 percent to enable high volume products.
Many of the apps require High Bandwidth Memory (HBM), another Jedec interface that is still in development. The HBM die will be paired with graphics processors or CPUs increase memory throughput and thus performance. McCann estimates first 2.5-D stacks using HBM could ship in low volumes in 2014.
In addition, Globalfoundries is working with one partner on a lower cost, lower bandwidth option using laminates instead of a silicon interposer. Nvidia also expressed interest in this approach recently.
Separately, Globalfoundries linked two functioning wafers using tens of thousands of TSVs in its New York fab. It gathered electrical verification data on the designs that used copper TSVs at 40- and 20-micron pitch.
McCann expressed optimism about the size of the TSVs and use of copper. In addition, so-called “keep out zones” around the TSVs “turned into a non issue for us,” he said.
“We started at five micron keep-out zones and then went down to 1-2 microns without seeing much impact on digital circuits,” he said. “We don’t need TSVs anywhere near analog circuits today, so we are keeping them away, but we will need to address them for future heterogeneous chips,” he added.
In its tests, the foundry only did limited modeling of thermal issues, expected to be a major challenge when packing processors next to memory. “Mostly that’s work being handled by our customers,” McCann said.
Click on image to enlarge.
Globalfoundries used 40 and 20 micron pitch TSVs in its wafer-level electrical tests.
TI got out of the smartphone market
I'm less sure about the ST/ST-Ericsson move but assume it was about that company's financial woes more than anything else.
Meanwhile apparently most of the big SoC makers have decided they don't want 28 nm WideIO 1.0 memory at 12G but 20nm WideIO 2.0 at 24G.
"rise above Moore's law"? I think not. the issue here is that numerous segments need 2.5d today, primarily because no one can afford the power and pins to drive enough memory. since this is a power-based argument, actual 3d stacking is mostly irrelevant: the need is many/wide pins from cpu to memory, and no cpu (except perhaps in a phone) can afford to be stacked, dissipation-wise.
memory-wall, meet interposer. that's what's on the table. it's not a fab issue either - denser single chips don't eliminate the need for 2.5d integration - if anything, it gets worse.
a refreshingly honest report on the status of 3-D stacking / 2.5 D modules that exposes the reality of this overly mechanical attempt to rise above Moore's Law or circumvent a bank balance too lean to afford a 14 nm Fab.
Though the partisans of 3-D stacking have for quite a few years now been drooling about the bonanza of the billion units a year Smart Phone industry adopting their technology "any time now", given the laws of physics & economics thats probably one of the last application that would ever happen. Per historical precedence the normal order of adoption for this complex process would be : military, medical, supercomputers, servers, graphics-heavy consumer systems like game systems and perhaps only then Tablets and Smart phones.
And even after all the hardware mfg. issues of 3-d stacks are solved, the architecture and programing issues of hooking up the right chunk of memory to a specific processor core in zillion - core processors would remain just as much a challenge as in any other parallel computer.
2.5 - d modules with Si interposers would provide good enough interconnect density and thus significant improvement in Bandwidth / Power eff. but these Interposers need to be much cheaper than just by 50 % ( Glo Fo target ? ) to prevent the time - tested strategy to integrate the whole shebang on a single chip.
Regarding 2.5-d modules with cheaper organic substrates, the improvement in bandwidth will be severely restricted by interconnect density possible even at future geometries ( 8 um L&S, 30 um dia via ) or no. of layers ( cost ). RC delay and signal skew in resulting long lines between chips would be significant. So not much of a improvement in Bandwidth or power efficiency there.
Elegant electrical methods to work around architectural and physical limits of package level integration are in development and would very likely precede the complex TSV based 2.5 or 3-D processes.
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