SANTA CLARA, Calif.--The industry lacks consensus on how to program the heterogeneous mobile SoCs now on the rise in smartphones and tablets. But the good news is some promising power-friendly techniques are starting to emerge.
Senior engineers from Nvidia and Qualcomm said there’s no resolution in sight for the fragmented ways to handle mixtures of CPU, GPU and DSP cores in today’s mobile chips. Among the options, Android backs Renderscript, Apple helped launch OpenCL and Microsoft is driving Windows Direct Compute.
“There are many APIs still evolving, so our approach is make sure our system infrastructure is prepped to deal with any of them,” said Bob Rychlik, a system architect at Qualcomm, speaking on a panel at the Linley Mobile conference here. “We are hoping with these open standards the industry will find some convergence,” he added.
Meanwhile, Qualcomm uses compiler tools from the LLVM Project to make its SoCs more adaptable to different programming models. In a talk here, Rychlik said traditional computer based MESI cache coherency models and context switching methods sometimes burn too much power for mobile chips.
“There are some apps where [traditional approaches are] great and many others where they should not be used,” he said. Meanwhile “there’s a renaissance in papers and upcoming interesting work on different ways to achieve cache coherency without the overhead of snooping and invaliding traffic,” he said.
Rychlik declined to provide specific references for new techniques well suited for mobile chips, saying Qualcomm was not ready to discuss its work in the area. However, he did refer to a February conference in Shenzhen and one last fall in Minneapolis that contained useful papers on the topic.
Qualcomm's use of, and motivations for, using LLVM, to me are the most interesting aspects of the article.
It would seem, in general, that letting the front end, in broad use environments, be useful in dictating the hardware resources, architecture and even the instructions available.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.