SAN JOSE, Calif. – Nick McKeown, an engineering professor at Stanford University, expects a new breed of merchant networking processors to replace ASICs in routers and switches over the next decade.
McKeown says he has looked into the future of communication processors “and if you squint hard it looks like RISC for networking.”
McKeown helped kick start the movement toward software-defined networking based on the OpenFlow protocol. Its goal is to enable a new class of software apps that manage gangs of simplified switches and routers.
If the effort succeeds it could ease and lower the cost of running large data centers and business networks. It will also disrupt the current business model based on expensive network gear that uses complex ASICs and proprietary code.
McKeown sees a new breed of merchant chips taking the place of the big ASICs companies such as Alcatel-Lucent, Cisco, Ericsson, Juniper and others design today. The first attempts at creating them likely will emerge over the next two or three years, he said.
In a research effort with Texas Instruments and others, McKeown created a prototype on paper of the new device. It essentially consists of a parsing engine that interprets the increasingly wide set of headers on each packet then pushes the packet into a pipeline of execution units that match patterns in the headers and take actions on them.
“It’s a brute force feed-forward pipe of match and action, match and action,” he said, relating work in a paper now under review for publication.
The paper reports that for 15 percent more silicon area and power such a chip could handle any current or future protocol at the same performance levels as today’s protocol-specific ASICs. McKeown predicts that in a decade the big router and switch players will have replaced their ASICs with such merchant chips and morphed into software companies.
“We’ll look back in 10 years and they will be providing control plane software and apps on top of it,” he said.
Two or three companies are said to be exploring such chips already including startup xPliant and existing players such as TI and possibly Cavium and Mellanox.
“Merchant silicon is one of the prime drivers of this movement,” said McKeown. “The incumbent chip vendors such as Broadcom and Marvell are adding OpenFlow support to their switches already--that’s what they should do, and they have been involved from the start,” he said.
Was the xelerated architecture talking about a completely protocol independent chip design ? Nick is talking about In-
silicon implementation of forwarding abstractions that has a general applicability to any type of communications forwarding problem.
You left a key leader in software defined networks off of your list....BROCADE COMMUNICATIONS. Brocade is using a combination of ASICs, FPGAs and high-performance network processors in many of their current products and has paved the way for SDNs ahead of our competitors!
A company called Spider Systems used to make network hardware (routers, bridges, terminal servers and SNMP probes) based on the Intel 386 and 960 processors back in the 1990's. Cisco then moved to custom ASIC's and RFC protocols. I have a couple of Squiggle magazines from this time.
nick should take a look at xelerated dataflow architecture which was created in 2000 - that solves the packet processing excatly like he is suggesting with a very deep pipeline of classify action blocks and has fully programmable dataflow processor element which gives hundred percent deterministic behaviour
so the new breed of network processors that nick wrote a paper on has been around for 13 years
xelerated was bought by marvell for a few years ago and is still til this date the only programmable npu that is deterministic by design
I am sure that ASICs will be around for a long time (longer than we expect anyway), but the trend has been away from full custom ASICs towards FPGAs/programmables for some time now. The cost in time and money to develop full custom ASICs has been the impetus for many designs to switch to FPGAs. Given the improved performance/cost/size of the current FPGA families with on die processors I would only expect this trend to continue. With the development of software defined networking and the time for it to mature it makes a logical next step. I wonder how many companies will be left behind..?
That's not fully correct. The IXP1200 (and I believe its predecessors), featured an ARM processor for control plane processing along with 6 microengine processors specialized for packet processing.
Still... this is interesting that it's coming up again.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.