It will be revolution by evolution as the new software and new hardware emerge in a chicken-and-egg dance.
The current 1.x versions of OpenFlow represent a compromise. “Ideally we would have started it as a generic match-and-action flow, but it had to be mapped on to existing chips—the next generation will be more protocol independent,” McKeown said.
Last year, the Open Networking Foundation (ONF) that oversees OpenFlow engaged ASIC makers in a so-called Forwarding Abstractions working group. It aimed to narrow the gulf between what OpenFlow wants to enable and what existing and planned ASIC do.
Now ONF is starting a new effort it calls a chip advisory board. “We will learn from them what’s possible [in silicon], and out of that will emerge what’s possible for the next generation of OpenFlow,” he said
OpenFlow began using content-addressable memories as an intermediary to interface to router and switch ASICs, but the approach limited its functionality. More recently it has used a technique of matching multiple tables.
“The protocol independent version [of OpenFlow] will take awhile,” McKeown said.
Was the xelerated architecture talking about a completely protocol independent chip design ? Nick is talking about In-
silicon implementation of forwarding abstractions that has a general applicability to any type of communications forwarding problem.
You left a key leader in software defined networks off of your list....BROCADE COMMUNICATIONS. Brocade is using a combination of ASICs, FPGAs and high-performance network processors in many of their current products and has paved the way for SDNs ahead of our competitors!
A company called Spider Systems used to make network hardware (routers, bridges, terminal servers and SNMP probes) based on the Intel 386 and 960 processors back in the 1990's. Cisco then moved to custom ASIC's and RFC protocols. I have a couple of Squiggle magazines from this time.
nick should take a look at xelerated dataflow architecture which was created in 2000 - that solves the packet processing excatly like he is suggesting with a very deep pipeline of classify action blocks and has fully programmable dataflow processor element which gives hundred percent deterministic behaviour
so the new breed of network processors that nick wrote a paper on has been around for 13 years
xelerated was bought by marvell for a few years ago and is still til this date the only programmable npu that is deterministic by design
I am sure that ASICs will be around for a long time (longer than we expect anyway), but the trend has been away from full custom ASICs towards FPGAs/programmables for some time now. The cost in time and money to develop full custom ASICs has been the impetus for many designs to switch to FPGAs. Given the improved performance/cost/size of the current FPGA families with on die processors I would only expect this trend to continue. With the development of software defined networking and the time for it to mature it makes a logical next step. I wonder how many companies will be left behind..?
That's not fully correct. The IXP1200 (and I believe its predecessors), featured an ARM processor for control plane processing along with 6 microengine processors specialized for packet processing.
Still... this is interesting that it's coming up again.