SAN JOSE, Calif. – Nick McKeown, an engineering professor at Stanford University, expects a new breed of merchant networking processors to replace ASICs in routers and switches over the next decade.
McKeown says he has looked into the future of communication processors “and if you squint hard it looks like RISC for networking.”
McKeown helped kick start the movement toward software-defined networking based on the OpenFlow protocol. Its goal is to enable a new class of software apps that manage gangs of simplified switches and routers.
If the effort succeeds it could ease and lower the cost of running large data centers and business networks. It will also disrupt the current business model based on expensive network gear that uses complex ASICs and proprietary code.
McKeown sees a new breed of merchant chips taking the place of the big ASICs companies such as Alcatel-Lucent, Cisco, Ericsson, Juniper and others design today. The first attempts at creating them likely will emerge over the next two or three years, he said.
In a research effort with Texas Instruments and others, McKeown created a prototype on paper of the new device. It essentially consists of a parsing engine that interprets the increasingly wide set of headers on each packet then pushes the packet into a pipeline of execution units that match patterns in the headers and take actions on them.
“It’s a brute force feed-forward pipe of match and action, match and action,” he said, relating work in a paper now under review for publication.
The paper reports that for 15 percent more silicon area and power such a chip could handle any current or future protocol at the same performance levels as today’s protocol-specific ASICs. McKeown predicts that in a decade the big router and switch players will have replaced their ASICs with such merchant chips and morphed into software companies.
“We’ll look back in 10 years and they will be providing control plane software and apps on top of it,” he said.
Two or three companies are said to be exploring such chips already including startup xPliant and existing players such as TI and possibly Cavium and Mellanox.
“Merchant silicon is one of the prime drivers of this movement,” said McKeown. “The incumbent chip vendors such as Broadcom and Marvell are adding OpenFlow support to their switches already--that’s what they should do, and they have been involved from the start,” he said.
"When a certain large semi chip supplier sold off their industry leading network processor business a few years ago"
If you are talking about Intel selling off Xscale, I heard that it was underpowered and power-hungry, (and difficult to program) and thus not really competitive with other chips on the market.
It was also based off of ARM processors. Intel may regret giving up ARM processor experience, but I think their network processor needed some work.
The question is not just "will ASICs be replaced in com gear" but "will ASICs be replaced (in everything)". I believe the writing is on the wall for ASICs. They are on the way out, squeezed from both ends by ASSPs and FPGAs. In ten years the ASIC industry will be a shadow of what it is today.
By the way, in today's high priced com gear most of the heavy lifting is done by FPGAs anyway. Yes, the high level software control still goes through the ASICs, but it is the FPGAs that push the packets forward to their destination.
I think that as CPUs become faster and faster, there is a very logical trend to do more in software and less in hardware. So this can be applied to IP routers as well.
My problem is mostly with hyping this up as "reinventing" anything. Much like software defined radio, what it does mostly to to increase flexibility and upgradeability. But it doesn't reinvent anything at all.
Well duh, I say :-) . What took so long? One only has to look at the history of the computer to see the exact same thing happening circa 1980. When a certain large semi chip supplier sold off their industry leading network processor business a few years ago I thought (and purely expressed the view ) that it was a very shortsighted move for the very same reasons. Time will tell whether Cisco is the DEC of the past 20 years.
Why not a hybrid chip that is predominantly "off the shelf" coupled with a good sized very fast internal FPGA?
The issue with a prediction such as this is not only do you have to predict where performance of merchant chips will go, but also predict where the future of networking may go. We can make assumptions about bit growth, but are all our other assumptions going to be right?