SAN FRANCISCO—Intel Corp. Monday (May 7) described its new low-power, high-performance microarchitecture, dubbed Silvermont, which will form foundation of 22-nm Atom SoCs available later this year.
Intel (Santa Clara, Calif.) said the Silvermont takes aim at the low-power requirements in market segments from smartphones to data centers. The Silvermont chips that will come to market later this year will be built on Intel's 22-nm process technology with tri-gates (also known as FinFETs), Intel said.
"Silvermont is a leap forward and an entirely new technology foundation for the future that will address a broad range of products and market segments," said Dadi Perlmutter, Intel executive vice president and chief product officer, in a statement.
Perlmutter said early sampling of Intel's 22-nm SoCs, including Bay Trail and Avoton SoCs, is already getting positive feedback from customers. "Going forward, we will accelerate future generations of this low-power microarchitecture on a yearly cadence," Perlmutter said.
Intel claims the Silvermont architecture delivers industry-leading performance-per-watt efficiency—a bold claim considering that ARM-based SoCs are generally regarded to have an significant power efficiency advantages when compared with Intel's X86 chips.
According to Intel, the wide dynamic range of Silvermont makes it more efficient than asymmetric cores.
According to Intel, compared to the current-generation Atom processor core, Silvermont delivers about 3X peak performance or the same performance at about 5X power over a variety of standard metrics.
Silvermont was designed and co-optimized with Intel's 22-nm SoC process using tri-gate transistors, Intel said. The chip firm claims the process offers a significant performance increase and improved energy efficiency.
"Through our design and process technology co-optimization we exceeded our goals for Silvermont," said Belli Kuttanna, Intel Fellow and chief architect.
"By taking advantage of our strengths in microarchitecture development and leading-edge process technology, we delivered a technology package that enables significantly improved performance and power efficiency–all while delivering higher frequencies," Kuttanna said.
I am not guessing.
Silvermount has ivy bridge graphics... (Big Si area) ...and Atom core with out of order execution ( significantly bloats x86 core size.)
We have look at this for smartphone application....I am telling you with certainty that silvermount is NOT going to ship in smartphones at any volume due to cost.
This is simple Intel marketing at it's finest....marketing leadership performance but using a lot of silicon area so its not apples to apples benchmarking
He has a point though, even the current Atom has a much larger die size than its competitors:
This is why there are 4, 5 and even 8-core ARMs but only dual Atoms.
Considering this subsidy example further Ivy E3 at 26/22 nm RISK production cost is approximately $0.53 mm2 on average marginal cost of $88, average marginal revenue $196, average weighed Price $279 (range $189 to $884). So some E3v2’s earn a much higher margin then ATOM does today.
In this example the average marginal cost of producing one additional E3v2 redirected to ATOM now delivers five 62 mm2 devices at fabrication cost of $15.95 each that is $0.26 mm2 at run end. If those 5 processors fetch $55.50 each can deliver the equivalent of one E3’s average margin in this $197 marginal revenue displacement.
The key question then is Intel’s variable cost of production, the general administrative and manpower charge to produce a single microprocessor, or in this general example the system component solution, which on Intel’s financial is around $105. Here raises the price below variable cost query.
Mike Bruzzone, Camp Marketing
Financial info like this from Bruzzer is too complex for me. But I do believe the issue is not about performance but cost. As mentioned before:
Ask Intel the die size. Intel typically has to be one generation ahead to have same die size. very expensive
Ask Intel about margins.... actually you can deduce them from the 10Q for the group that runs Atom.
If these numbers have anything to do with reality then they are confidential information. Hence, either this is all guess BS, or you are violating your NDA with Intel (which they do not look at kindly, and rightfully so). My guess is that you know nothing and made up these numbers.
You know, Intel has been in the chip business for 40+ years, so one must assume that they understand basics like die size, die cost, gross margin, etc. If I was ARM or TSMC I would be very worried. Intel (not unlike the US) is slow, and certainly does not do the right thing many times, but when it starts moving you better get out of the way.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.