SAN FRANCISCO—Intel Corp. Monday (May 7) described its new low-power, high-performance microarchitecture, dubbed Silvermont, which will form foundation of 22-nm Atom SoCs available later this year.
Intel (Santa Clara, Calif.) said the Silvermont takes aim at the low-power requirements in market segments from smartphones to data centers. The Silvermont chips that will come to market later this year will be built on Intel's 22-nm process technology with tri-gates (also known as FinFETs), Intel said.
"Silvermont is a leap forward and an entirely new technology foundation for the future that will address a broad range of products and market segments," said Dadi Perlmutter, Intel executive vice president and chief product officer, in a statement.
Perlmutter said early sampling of Intel's 22-nm SoCs, including Bay Trail and Avoton SoCs, is already getting positive feedback from customers. "Going forward, we will accelerate future generations of this low-power microarchitecture on a yearly cadence," Perlmutter said.
Intel claims the Silvermont architecture delivers industry-leading performance-per-watt efficiency—a bold claim considering that ARM-based SoCs are generally regarded to have an significant power efficiency advantages when compared with Intel's X86 chips.
According to Intel, the wide dynamic range of Silvermont makes it more efficient than asymmetric cores.
According to Intel, compared to the current-generation Atom processor core, Silvermont delivers about 3X peak performance or the same performance at about 5X power over a variety of standard metrics.
Silvermont was designed and co-optimized with Intel's 22-nm SoC process using tri-gate transistors, Intel said. The chip firm claims the process offers a significant performance increase and improved energy efficiency.
"Through our design and process technology co-optimization we exceeded our goals for Silvermont," said Belli Kuttanna, Intel Fellow and chief architect.
"By taking advantage of our strengths in microarchitecture development and leading-edge process technology, we delivered a technology package that enables significantly improved performance and power efficiency–all while delivering higher frequencies," Kuttanna said.
Except that you might wonder if the mobile industry is waiting for a giant like Intel with the same tactics as the PC industry to step in. Remember that the mobile market is somewhat vertically integrated (Apple, Samsung) and at the bottom you have the low-cost players like Mediatek.
Probably the company to loose the most is Qualcomm.
Ask intel about silvermount die size. Word on street is die size is not competitive and hence silvermont is not competitive on cost and will have little impact on smartphone and tablet market.
Ask intel what was the die size of the silvermount chip vs the die size of the parts intel benchmarked against.
About 2X larger die size for intel !!!
I can't believe market falls for intel marketing hook line and sinker. Just look at last years intel marketing claims on how great ivy bridge was going to be for power using "revolutionary process technology". Claims were ivy bridge would reduce Operational power by 50% and leakage power by 10x and we got 0 (no improvement) for both
Mark my word. When market sees silvermount die size ... " market will realize intel process technology is not so "revolutionary"
Look what is all ready known.
Silvermount has design port of a Ivy bridge GPU plus 4 fat X86 cores.
With above you can estimate die size.
No way that can have a die size to be competitive in a smartphone. on top of that it does not have integrated baseband.
All I am suggesting is to benchmark die size. It will soon be clear
Intel's "revolutionary manufacturing" is not competitive for smartphone market
Valleyview = atom with ivy bridge graphics.
Per Anand (link below) and intel executives have also made this statement.
....point being ---silly this article and many articles think this is viable for smartphone.
No question performance is great but that is meaningless when using too much silicon area to sell for smartphone asp.
I am not guessing.
Silvermount has ivy bridge graphics... (Big Si area) ...and Atom core with out of order execution ( significantly bloats x86 core size.)
We have look at this for smartphone application....I am telling you with certainty that silvermount is NOT going to ship in smartphones at any volume due to cost.
This is simple Intel marketing at it's finest....marketing leadership performance but using a lot of silicon area so its not apples to apples benchmarking
You're shameless to the extreme,INTEL 22 Indeed not perfect, such as thermal issues but from snb to ivb , DIE SIZE 216MM--160MM TDP 95W-77W, The main purpose is reached,A15 Touches was a disaster,TI IS OVER,
You know, Intel has been in the chip business for 40+ years, so one must assume that they understand basics like die size, die cost, gross margin, etc. If I was ARM or TSMC I would be very worried. Intel (not unlike the US) is slow, and certainly does not do the right thing many times, but when it starts moving you better get out of the way.
He has a point though, even the current Atom has a much larger die size than its competitors:
This is why there are 4, 5 and even 8-core ARMs but only dual Atoms.
How many times Intel announced something superior, just to make customers wait and not buy a product of a competing company?
How many times Intel manipulated benchmarks?
Look at the facts:
* Intel does not name the competitors (neither Architecture, nor process, nor maker)
* Intel does not explicitly stated, what has been compared (did they compare the power consumption of a mere core to a complete ARM SoC)
As soon as mobilephones / tablets using that Silvermont SoC are available for everyone, we can try these gadgets ourselves and then know how these perform.
I found the analysis very interesting. A lot of the applications will depend upon the support tools that Intel provides to support the chips. If they can do as well as Cypress has on their PSOC, then Intel might have a verying interesting device.
When do we get more specifics on Rangeley and Avoton. They are the more interesting SOCs announced. Everyone is gunning for the mobile space, the low power server and telecom infrastructure plays don't get the same attention.
Yes, Chinese dual cores are around $5, quad around $9. These are Cortex-A7 or Cortex-A9 based and run at 1.0-1.2GHz. Not top performance of course but more than fast enough for mid-range phones and tablets.
If they could place these when they come out @ $20 in 1X on Avnet.com @ 3 watts I would be shocked... I think that price and power cuts are the only way to dent the embedded market... Until then it's not possible... Current atom processors are $30-60 in that range, and more for the newer ones... It might as well be in a PC with that cost... The most popular ARM are dual core 1 watt CPUs... In fact 300mW-700mW is the battery powered pocket device range... You could still get by on 1 watt at that range but you will probably have to charge a lot ( unless you use a laptop battery system, power bricks, which by that time you're not in the low power segment, you're using a laptop processor by then. )... Complete opposite in the device world is an altera max II z which is actually considered a 'zero-power' device in the embedded market... In the PC world though people think low power is 10-65 watts... It's a far cry from low power. It's more of a metaphorical/consumer/box sticker term for customers of tablets/laptops. I mean everyone loves to see the words low power, but it's not necessarily that easy to explain... I personally feel risky going over 3 watts. If my CPU is over 3 watts then I will look at the block diagram and see if the features are important. As soon as it's up to 10 watts it should be on par with low-end PC or people will buy a laptop or something else instead...
Reading this article, Silvermont is "better" "best-in-class" "better dynamic range", "well positioned to enable great products and experiences across the full spectrum of computing" ....
Fluff marketing as usual. Does anyone have real benchmark/ measured power /cost information?
Intel is about to diversify ATOM into many derivatives all of which are capable on their performance too displace Xeon E3, and Performance Mobile, if only the application’s software, and the internal politics of democratic capitalism. Lest not the antitrust considerations; Areeda Turner for one.
So it’s important to understand on overhead that Intel cannot afford to produce any of these ATOM products. Which is why their dice size are increasing by feature set to offer price/performance levels capable of yielding a displacement product’s margin potential on their cost price ratio. This evolution takes into account much more than that old standby which is ever larger L2 caches.
Dice that are less than 100 mm2 impose a financial burden on Intel; economically, if their performance does not equate to a price point that offsets their long run cost.
Intel’s fully burdened cost of production for a dual core microprocessor is no less than $0.24 per mm2, and for Quads averages in the $0.33 mm2 range. Multi core, large cache, many metal layers cost more which is why they are currently fabricated through run down. Where ATOM, up until now appears to be wafer starts run end.
The marginal cost of 20.833 Million ATOMs produced Sandy run end through Ivy ramp is $2.16. But this is not a cost in the typical view; it is an opportunity cost to produce or not to produce. That is because that $2.16 actually represents $18.10 in lost revenue, over the production long run, subsidized by all other products that do make a profit. The average marginal revenue loss from this opportunity cost is $15.95 or for a 62 mm2 device, $0.25 per mm2.
Mike Bruzzone, Camp Marketing
If these numbers have anything to do with reality then they are confidential information. Hence, either this is all guess BS, or you are violating your NDA with Intel (which they do not look at kindly, and rightfully so). My guess is that you know nothing and made up these numbers.
Financial info like this from Bruzzer is too complex for me. But I do believe the issue is not about performance but cost. As mentioned before:
Ask Intel the die size. Intel typically has to be one generation ahead to have same die size. very expensive
Ask Intel about margins.... actually you can deduce them from the 10Q for the group that runs Atom.
Considering this subsidy example further Ivy E3 at 26/22 nm RISK production cost is approximately $0.53 mm2 on average marginal cost of $88, average marginal revenue $196, average weighed Price $279 (range $189 to $884). So some E3v2’s earn a much higher margin then ATOM does today.
In this example the average marginal cost of producing one additional E3v2 redirected to ATOM now delivers five 62 mm2 devices at fabrication cost of $15.95 each that is $0.26 mm2 at run end. If those 5 processors fetch $55.50 each can deliver the equivalent of one E3’s average margin in this $197 marginal revenue displacement.
The key question then is Intel’s variable cost of production, the general administrative and manpower charge to produce a single microprocessor, or in this general example the system component solution, which on Intel’s financial is around $105. Here raises the price below variable cost query.
Mike Bruzzone, Camp Marketing
Join our online Radio Show on Friday 11th July starting at 2:00pm Eastern, when EETimes editor of all things fun and interesting, Max Maxfield, and embedded systems expert, Jack Ganssle, will debate as to just what is, and is not, and embedded system.