SAN FRANCISCO—Intel Corp. Monday (May 7) described its new low-power, high-performance microarchitecture, dubbed Silvermont, which will form foundation of 22-nm Atom SoCs available later this year.
Intel (Santa Clara, Calif.) said the Silvermont takes aim at the low-power requirements in market segments from smartphones to data centers. The Silvermont chips that will come to market later this year will be built on Intel's 22-nm process technology with tri-gates (also known as FinFETs), Intel said.
"Silvermont is a leap forward and an entirely new technology foundation for the future that will address a broad range of products and market segments," said Dadi Perlmutter, Intel executive vice president and chief product officer, in a statement.
Perlmutter said early sampling of Intel's 22-nm SoCs, including Bay Trail and Avoton SoCs, is already getting positive feedback from customers. "Going forward, we will accelerate future generations of this low-power microarchitecture on a yearly cadence," Perlmutter said.
Intel claims the Silvermont architecture delivers industry-leading performance-per-watt efficiency—a bold claim considering that ARM-based SoCs are generally regarded to have an significant power efficiency advantages when compared with Intel's X86 chips.
According to Intel, the wide dynamic range of Silvermont makes it more efficient than asymmetric cores.
According to Intel, compared to the current-generation Atom processor core, Silvermont delivers about 3X peak performance or the same performance at about 5X power over a variety of standard metrics.
Silvermont was designed and co-optimized with Intel's 22-nm SoC process using tri-gate transistors, Intel said. The chip firm claims the process offers a significant performance increase and improved energy efficiency.
"Through our design and process technology co-optimization we exceeded our goals for Silvermont," said Belli Kuttanna, Intel Fellow and chief architect.
"By taking advantage of our strengths in microarchitecture development and leading-edge process technology, we delivered a technology package that enables significantly improved performance and power efficiency–all while delivering higher frequencies," Kuttanna said.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.