TSMC revealed its official roadmap for monolithic CMOS earlier this year, starting with advanced planar SoCs at the 20-nanometer in 2013, using double-patterning without the need for direct coloring by virtue of its novel method of avoiding G-rule violations. TSMC will follow up with FinFET transistors at the 16-nanometer node by 2014, using low power-supply voltages -- 0.8- down to 0.6-volts -- thus enabling ultra-low-power processors, such as an ARMv8 that consumes as little as 750-milliWatts. Next TSMC plans to transfer its FinFETs to the 10-nanometer node by 2015 to 2016 to yield a 35 percent speed gain, using either direct-write multiple e-beams or possibly extreme-ultra-violet (EUV), which it is developing with ASML (Advanced Semiconductor Materials for Lithography).
"We have already demonstrated EUV with our preproduction tools in-house, and our early production tools are now being installed. At this point the availability of the light-source is the main obstacle, along with some other technical issues to be resolved such as the mask color code and operating in a vacuum system, and of course there is always a steep learning curve for any new lithography," said Sun.
Closer to the manufacturing floor is e-beam lithography, which TSMC has been perfecting with Mapper Lithography, using multiple beams for direct-write lithography in novel patterns that avoid hot spots while maintaining the high-throughput necessary to make it commercially feasible.
"We are championing multi-bean direct-write e-beam lithography, demonstrating its feasibility with partners right now and making solid progress, including some prototypes that are showing a lot of promise," said Sun. "For instance, instead of using a raster like when using a single beam, you can have block-like patterns for each beam to follow that are very similar -- enabling the same data paths to feed the multiple beams."
Yet more experimental that e-beam and EUV are new techniques and materials to TSMC hopes to perfect at the 7-to-5 nanometer node in time to put it ahead of the pack. At these advanced nodes the transistors channels will have to be made either of silicon nanowires or possibly from III-V materials, such as indium arsenide (InAs) deposited on a silicon substrate. TSMC is holding its cards near its vest at these advanced nodes, but claims to see a clear path to 5-nanometer operating at voltages as low as 0.5 volts in as little as 10 years.
Few topic come to mind if there is a follow up to this article with TSMC:
-what is TSMC's plan to bring the costs down in 3D IC integration?
-why isn't TSMC actively promoting / nurturing ecosystem partners that can perhaps develop cost-effective technologies (such as interposers, cooling technologies, etc) than organic efforts?
-is there a product vision / road map for heterogeneous integration?
Sure 10nm can be done with ebeam....but at what cost is the right question.
Not cost effective for mainstream SOC. moores law roadmap is becomming clearer. 28nm is lowest cost per transistor and where bulk of cost sensitive SOC made
Chipmonk - you posted this back in November and you were right on the money.
3D is too costly for low priced SoCs
"Haswell is going to be a 2.5 d module with the Level 4 cache chip next to the processor, the chips connected by fine-pitch high-density thin film interconnects on the Si substrate of the module. Will have lots of interconnects, enabling lots of parallelism in memory accesss by multi - core in CPU / SoC. BTW won't be able to stack chips ( true 3D ) because need to take heat out of the 10 watt CPU."
TSMC is right in finally accepting that there is a long way to go in terms of design methodology yield improvement etc. before they can hope to use 3D die stacking for jelly - bean like Smart Phones. Since they seem to be putting a lot of their competitive eggs ( vis a vis Intel ? ) into the basket of stacking dissimilar dice by 3D, wish the EE Times reporter had quizzed them on specifics and not let them get away with "motherhood" type statements.
Oh well !
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