However, just as important as advanced node CMOS, according to Sun, is using 3-D to tie these advanced chips together with all the other analog and mixed-signal capabilities demanded by mobile systems. The first users of its 3-D super-chip concept, however, will be high-performance systems -- with the knowledge achieved there transferred to high-volume applications a few years later. In the meantime, other more economical wafer-scale techniques will be used by high-volume applications, such as its Chip on Wafer on Substrate (CoWoS) which uses TSVs to integrate multiple chips into a single super-package, such as DRAMs atop SoCs.
"We have already been working on 3-D for quite a while, and have demonstrated certain capabilities, published papers on stacking die, such as stacking DRAM die on top of logic chips and have demonstrated memory cubes, so from a technical feasibility standpoint many capabilities have already been developed," said Sun. "When it comes down to production, however, 3-D will first be used in high-end high-performance systems such as FPGAs, networking and graphic systems, which will present the entry point, along with adding more memory and other things with interposers. However, in the end 3-D must be made cost-effective if it is to be used in mobile systems. 3-D is ideal for smartphones in terms of packaging, and we have already demonstrated some design considerations, but from the production stand point it will be later. In the meantime, we have other package-on-package solutions that have already been refined for high-volume manufacturing. TSMC will have all these available, it is just a matter of which customers will be willing to pay for it, because in the end it will be the right-product, with the right-value, for the right price."
TSMC's long-term goal is to use 3-D super-chip integration to emulate the human brain, which Sun said runs on just 20-watts. To achieve that level of 3-D super-chip integration will require a 200-times shrink over today, which he estimates will be at least seven generations away, at about the 2-nanometer node circa 2028.
TSMC is right in finally accepting that there is a long way to go in terms of design methodology yield improvement etc. before they can hope to use 3D die stacking for jelly - bean like Smart Phones. Since they seem to be putting a lot of their competitive eggs ( vis a vis Intel ? ) into the basket of stacking dissimilar dice by 3D, wish the EE Times reporter had quizzed them on specifics and not let them get away with "motherhood" type statements.
Oh well !
Few topic come to mind if there is a follow up to this article with TSMC:
-what is TSMC's plan to bring the costs down in 3D IC integration?
-why isn't TSMC actively promoting / nurturing ecosystem partners that can perhaps develop cost-effective technologies (such as interposers, cooling technologies, etc) than organic efforts?
-is there a product vision / road map for heterogeneous integration?
Chipmonk - you posted this back in November and you were right on the money.
3D is too costly for low priced SoCs
"Haswell is going to be a 2.5 d module with the Level 4 cache chip next to the processor, the chips connected by fine-pitch high-density thin film interconnects on the Si substrate of the module. Will have lots of interconnects, enabling lots of parallelism in memory accesss by multi - core in CPU / SoC. BTW won't be able to stack chips ( true 3D ) because need to take heat out of the 10 watt CPU."
Sure 10nm can be done with ebeam....but at what cost is the right question.
Not cost effective for mainstream SOC. moores law roadmap is becomming clearer. 28nm is lowest cost per transistor and where bulk of cost sensitive SOC made
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