Breaking News
News & Analysis

ST's strategy is a tale of two segments

Committed to exploiting Crolles technology
5/16/2013 04:28 PM EDT
3 comments
NO RATINGS
1 saves
< Previous Page 2 / 2
More Related Links
View Comments: Threaded | Newest First | Oldest First
kjdsfkjdshfkdshfvc
User Rank
Author
re: ST's strategy is a tale of two segments
kjdsfkjdshfkdshfvc   5/17/2013 3:42:06 PM
NO RATINGS
He looks like that dude from Heroes. http://bit.ly/IC4m9t

fredfog
User Rank
Author
re: ST's strategy is a tale of two segments
fredfog   5/18/2013 2:03:46 PM
NO RATINGS
too bad he is not a hero at all..

Chipguy1
User Rank
Author
re: ST's strategy is a tale of two segments
Chipguy1   5/20/2013 12:17:27 PM
NO RATINGS
One 300mm fab split into 3 areas with 1/3 being for FDSOI will not have scale to compete on cost in global market against big players The "Analysis" are smarter then the ST executives which do not seem to understand the semiconductor industry?

Most Recent Comments
michigan0
 
SteveHarris0
 
realjjj
 
SteveHarris0
 
SteveHarris0
 
VicVat
 
Les_Slater
 
SSDWEM
 
witeken
Most Recent Messages
9/25/2016
4:48:30 PM
michigan0 Sang Kim First, 28nm bulk is in volume manufacturing for several years by the major semiconductor companies but not 28nm FDSOI today yet. Why not? Simply because unlike 28nm bulk the LDD(Lightly Doped Drain) to minimize hot carrier generation can't be implemented in 28nm FDSOI. Furthermore, hot carrier reliability becomes worse with scaling, That is the major reason why 28nm FDSOI is not manufacturable today and will not be. Second, how can you suppress the leakage currents from such ultra short 7nm due to the short channel effects? How thin SOI thickness is required to prevent punch-through of un-dopped 7nm FDSOI? Possibly less than 4nm. Depositing such an ultra thin film less then 4nm filum uniformly and reliably over 12" wafers at the manufacturing line is extremely difficult or not even manufacturable. If not manufacturable, the 7nm FDSOI debate is over!Third, what happens when hot carriers are generated near the drain at normal operation of 7nm FDSOI? Electrons go to the positively biased drain with no harm but where the holes to go? The holes can't go to the substrate because of the thin BOX layer. Some holes may become trapped at the BOX layer causing Vt shift. However, the vast majority of holes drift through the the un-dopped SOI channel toward the N+Source,...

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
Like Us on Facebook
EE Times on Twitter
EE Times Twitter Feed