Samueli said he has briefed customers that prices for leading edge chips will increase, starting with the 20 nm generation due to rising fabrication costs. Market watcher Gartner Inc. recently estimated the average 45,000 wafer/month fab could pay a premium of about $500 million per process node due to the need to use two or more lithographic exposures to etch finer lines.
Stacking chips into so-called 3-D ICs promises a one-time boost in their capabilities, “but it’s expensive,” said Samueli. Broadcom expects to use 3-D stacks to add a layer of silicon photonics interconnects to its high end switch chips, probably starting in 2015 or later, he said.
“We are talking with potential [3-D IC] partners, but we don’t have it all sorted out yet,” he said.
Another industry veteran and EE on a panel with Samueli took issue with the Broadcom exec’s predictions. “The real situation is we have 10-15 years visibility and beyond that we just don’t know how we will solve [the problems of CMOS scaling] yet,” said Dave House, chairman of switch maker Brocade and a veteran of 23 years at Intel.
At Intel, House interacted regularly with Intel co-founder Gordon Moore who articulated the theory that roughly every two years chip makers would be able to double the number of transistors on a CMOS chip.
“In the 1970s I started preaching Moore’s Law will solve all our problems, and Gordon stopped me and said, ‘Ten years out, I don’t think it can continue,’” House said. “Ten years later, Gordon said again, ‘I only see about ten years here.’
“It became a regular thing at Intel strategic meetings where Gordon would say beyond ten years I don’t see it continuing,” said House who is also an EE by training. “As time went on there was always enough money spent and smart scientists” to solve CMOS scaling issues, he said.
“It could be we will have a firm barrier [at 5 nm], but I wouldn’t bet on it [because] the consequences will be so severe” he added.
In conversation after the event, Bob Metcalfe, one of the original inventors of Ethernet and the keynoter of the event shared his thoughts with Samueli and others.
“One of the big things I learned today is Moore’s Law is related to the elasticity of bandwidth—it not only creates the machines that need more bandwidth, it also creates the machines that provide that bandwidth,” he told Samueli. “If you are right and Moore’s Law ends, so will this bandwidth elasticity,” Metcalfe said.
Ethernet co-inventor Bob Metcalfe chatted with (from left) Andy Bechtolsheim of Arista, Bethany Mayer of HP and Henry Samueli of Broadcom.
I have seen a few presentations on quantum computing. In theory, this could replace CMOS and bring a whole new revolution to computing. Or it could be a big fat nothing like high temp superconductors and magnetic memory. It will probably be ten years before they know which one it will be.
If you look at the design rule specifications Taiwan Semiconductor is releasing and estimated 20 and 16 wafer prices, the Moore's law slow down is in full steam.
Progress will still happen. Just not by moving to designs to 20 and 16.
What is interesting Broadcom CEO must have similar numbers I have seen so this is not some academic. It is real data on Moore's law.
Intel also has a cost problem. They just don't know it since they sell 100 to 1000 CPUs. Intel has never successfully competed in its 50 year history on cost in a commodity market and is in for a rude awaking in mobile
Agree with Henry. all these times academics who said it is over, now the real people who are doing the job.
Still has 10 years. Do not underestimate our younger generation..they are smarter than us and they will come up with something, perhaps not simple CMOS..
Slow down your drinking check your designated driver (hope he/she is sobber) and cheers/salute for CMOS for all the years of work horse (at least kept me going on my entire carrier).
A few weeks ago, I wrote a blog for the All-Programmable-Planet --APP-- community in which one of the main issues was how Moore's law has started running out of gas in the last years.
It includes some graphics that illustrate that a speed limit has already been reached by analyzing Intel's CPU performance evolution along the time.
If someone is interested, follow the next link:
The cost of chip fabrication is rising as we speak with double patterning litho required below 20nm.
As for demand, may I remind you of Google Project Glass and other worn computing initiatives coming on as well as the trend to IoT/M2M.
Everything is getting sensed, instrumented, stored and analyzed. This will drive a new level of compute, storage, networking and bandwidth needs over the next 10-15 years as our current CMOS technology sputters.
I don't think scaling will suddenly hit a wall, I think it will be a long slow deceleration that has already started. Intel's 14nm FinFet is a very complicated, expensive process, which seems to deliver density but no added performance and no improvement in leakage. It uses a lot of brute force techniques like double patterning. So what are the consequences of a halt in Moore's law? The article discussed 3-d stacking, and optical chip connections. Does that mean the profits of Intel and TSMC will stagnate? That software developers will shoulder the load for performance improvement?
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.