SAN JOSE, Calif. Ė Intel will pack a voltage regulator on to its next generation Haswell processor, eliminating as many as seven external third party chips. The news was one of a few details Intel revealed in a Haswell briefing the same day its archrival Advanced Micro Devices announced three mobile processors.
Intel sketched out several steps it took to lower power consumption in Haswell, its next generation x86 processor geared for everything from 7W tablets to 75W servers. The techniques included integrating a voltage regulator, enhancing its 22nm process and using new power planes and states. It previously disclosedHaswell also will use a new on-chip DRAM.
Power is a major focus for Intel given its rising competition especially in tablets and servers with generally lower power chips based on ARM cores. Intel likely gave up the possibility of higher data rates in Haswell to capture the power savings. The first Haswell chips are expected to ship later this year.
Some Haswell chips will put two die in a package. The second die will be an integrated north and south bridge chip connected to the main CPU using a new low power interconnect.
All Haswell chips will sport an on-chip voltage regulator. It will combine what was in previous CPUs as many as seven external voltage regulators made by third parties, lower the bill of materials and motherboard footprint, said Rani Borkar, general manager of the Intel Architecture Group which designs the companyís main processors.
Gartner Inc. pegs the market for Intel Vcore regulators at roughly $325 million. It is slowly declining due price erosion of the components and declines in the overall PC market, said Stephan Ohr, Gartner analyst for analog and power chips.
The three largest vendors of the chips are ON Semiconductor, Intersil and Texas Instruments, according to Gartner. Linear Technology, Infineon, Maxim, Volterra and International Rectifier also participate in at least some segments such as voltage regulators for servers.
Over the past year, Haswell chip design teams worked with Intelís fab teams to optimize the version of its 22nm process, called P1270, used for the x86 chips. Intel would not describe the enhancements, but it said their effect was to lower transistor leakage by 2-3x compared to its previous Ivy Bridge generation while lowering its minimum voltage level (Vmin) and not reducing the chipís frequency.
The on-chip DRAM block is a novel design geared to serve the embedded Iris Pro graphics in Haswell. It is not a general purpose DRAM, said Kaizad R. Mistry, a vice president in Intelís technology and manufacturing group.
Intel uses a separate version of its 22nm process, called P1271, for its low power SoCs such as the Atom-based Silvermont. This process is the basis of what Intelís foundry customers use, Mistry said.
Overall, Haswell will deliver about 50 percent better battery life than the prior Ivy Bridge on active workloads while doubling graphics performance, Intel claimed. ďIt has content creation performance at power levels generally associated with content consumption devices,Ē said Borkar.
@Frank Eory: I had the same question. The article is unfortunately not detailed enough discern if PMIC functions are integrated. I think it makes more sense to leave those functions (driving and switching) seggregated from a board-level power management perspective.
True. But there're more to consider.
The more integrated your solution is, the less likely it would be flexible and cost- effective to your end users and this commodity market! You may argue that it is just a matter of time for the cost and flexibility to be of no issue, and you are right, it is just a matter of TIME for the chips to be a commodity. :)
Integration is the theme for everything now. When power management integrated the FETs, power stage engineers started to look for jobs; now it's the time for power engineers to think bigger than what we are doing right now.
I wonder whether it's just integration of a voltage regulator, or a complete power management system. If Intel has reached the point where they have integrated the essential PMIC functions, that is quite a big leap forward for them.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for todayís commercial processor giants such as Intel, ARM and Imagination Technologies.