The cost of designing system-on-chip silicon at 28-nm went up by 78 percent over the previous node, but the software cost was larger and more than doubled, says Semico Research.
Semico reckons the cost of developing the software that it is necessary to ship with system chips is now greater than the cost of the IC design.
While the cost of SoC design at the 28-nm node is 78 percent more than it was at the 40-nm node the cost of writing and checking the necessary software went up by 102 percent, the market researcher claims.
And the software burden will increase close to doubling in cost every year. Semico predicts a compound annual growth rate for SoC software development of 79 percent through to the arrival of the 10-nm chip manufacturing node. The cost to integrate discrete IP blocks used in contemporary SoCs is also rising showing a CAGR of 77.2 percent, Semico said.
The good news for chip developers is that Semico forecasts that the growth of chip design cost will be lower. Semico said it expects SoC design costs to increase 48 percent at the 20-nm node compared with the 28-nm node. They are expected to increase by a further 31 percent at the 14-nm node and by 35 percent at the 10-nm node.
Because of the high software burden and the cost of integrating IP cores from multiple sources the highest costs are seen in advanced multicore designs that break in a new process node. Derivative SoC designs at the same process node are a fraction of the cost of those first-time designs Semico said.
At the same time novel designs that are designed for an established manufacturing node will show a marked reduction in cost over time. The costs for an advanced performance multicore SoC design, continuously done at the 45-nm node will experience a negative CAGR of 12.7 percent by the time the 14-nm process node becomes commercially available.
Semico estimates that an made in 20-nm silicon that sells for $20 must ship 9.2 million units and achieve more than $180 million in revenue to breakeven.
I'm not sure what you're asking.
Revenue is total sales. Expenses are total costs. Profit is the difference between the two, if revenue *is* greater than expenses. (You sure hope it is...) Margin is the percentage difference between revenue and expenses.
As a general rule, you want the highest margin you can get, but what you can get will be constrained by market forces like competition from other vendors.
I don't have solid figures available, but I'm guessing that "overhead" in the sense I mentioned above will be the vast majority of expenses. (And overhead also includes things like salaries for the workers and applicable taxes.)
The bigger question is what the margin will be, and whether it will be high enough to justify producing the part. Depending on what you are making, you may be better served not to make that part, and concentrate your efforts on things where you can get a higher margin.
A good part of that decision will be based on anticipated sales volume. The more you can sell of something, the cheaper you can price it, and you can accept a lower margin because you have volume. If the market is smaller, you must charge more and get a higher margin to have the required profitability.
"How much profit is enough?" has a simple answer. Semiconductor electronics is a capital intensive business. It costs an enormous amount to build a fab and acquire the needed software, and you get the funds from elsewhere. The capital will have a cost, and the answer to "How much profit is required?" is "Enough to cover your marginal cost of capital."
@Peter: "One might assume that at 28-nm the breakeven volume would be lower, say 5 million units"
Why should the breakeven point be *lower* at 28mm? If anything, I'd guess the reverse.
As process geometries shrink, costs rise dramatically. The equipment needed to *make* the chips becomes a lot more expensive (and we get an increasing amount of consolidation and companies going fabless because the fabs are so expensive to build that few single companies can *afford* to.) And the software needed becomes more expensive even faster. The main cost of any chip is an amortized fraction of the costs of building the fab and buying the software.
Geometries shrink and parts get smaller, but the cost of the materials that make the part is an insignificant fraction of the cost of making it. Smaller part size does not lead to lower costs and lower breakeven points, because all of the other costs are much greater. Making it smaller does not, ipso facto, make it cheaper, because of the nature of the production process,
What drops costs is volume. The more of a part you can make, the smaller the allocated share of the overhead of making it can be, and the cheaper you can price it.
So another good reason to consider porting legacy bulk designs to FD-SOI: no redesign required, and scaling through 10nm. ST did complete 28nm bulk-to-FDSOI port in under 6 months with phenomenal results. Now they're aiming to hit 14nm FD-SOI before anyone does it in FinFET. See http://www.advancedsubstratenews.com/2013/06/which-will-hit-the-14nm-jackpot-first-fd-soi-or-finfet-gauntlet-down-race-on-2/ . Wonder if Semico considered it from this vantage point?
Well Semico came up with this figure of 9.2 million units to reach breakeven for $20 part in 20-nm. Actually they said 9.238 million units, which seems pointlessly precise.
One might assume that at 28-nm the breakeven volume would be lower, say 5 million units.
However, you make the point that at 28-nm the chip will be smaller than at 40-nm. But the fact is that usually the die size is the same (about 1 square centimeter) and companies integrate more functionality (and software) at the next node.
There is some area/cost benefit of shrinking a fixed design but it is done less often these days. ...Indeed at 20-nm there will be no area/cost benefit to moving to 16/14 FinFET's as the BEOL is the same and the die area will be the same.
Thanks for reply. Here are my thoughts. I feel your cost increasing from 40nm to 28nm could be a little misleading. From your comments, the most cost increase is due to deeper integration in 28nm SoC chip. And those similar cost was there before even in 40nm but it just shifted from system manufacturers to chip manufacturers in 28nm. With single chip used by multiple system manufacturers, it could end up development cost saving as well.
As hardware engineer, I am really interested in how much development cost difference between 28nm and 40nm with the same feature and requirements for typical SoC, for example mobile SoC. I am sure 28nm costs more but wondering how much. 28nm will have smaller die so it will have low unit cost to manufacture. So I am even more interested in knowing what is minimum quantity in 28nm to offset NRE cost from 40nm to 28nm.
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