The cost of designing system-on-chip silicon at 28-nm went up by 78 percent over the previous node, but the software cost was larger and more than doubled, says Semico Research.
Semico reckons the cost of developing the software that it is necessary to ship with system chips is now greater than the cost of the IC design.
While the cost of SoC design at the 28-nm node is 78 percent more than it was at the 40-nm node the cost of writing and checking the necessary software went up by 102 percent, the market researcher claims.
And the software burden will increase close to doubling in cost every year. Semico predicts a compound annual growth rate for SoC software development of 79 percent through to the arrival of the 10-nm chip manufacturing node. The cost to integrate discrete IP blocks used in contemporary SoCs is also rising showing a CAGR of 77.2 percent, Semico said.
The good news for chip developers is that Semico forecasts that the growth of chip design cost will be lower. Semico said it expects SoC design costs to increase 48 percent at the 20-nm node compared with the 28-nm node. They are expected to increase by a further 31 percent at the 14-nm node and by 35 percent at the 10-nm node.
Because of the high software burden and the cost of integrating IP cores from multiple sources the highest costs are seen in advanced multicore designs that break in a new process node. Derivative SoC designs at the same process node are a fraction of the cost of those first-time designs Semico said.
At the same time novel designs that are designed for an established manufacturing node will show a marked reduction in cost over time. The costs for an advanced performance multicore SoC design, continuously done at the 45-nm node will experience a negative CAGR of 12.7 percent by the time the 14-nm process node becomes commercially available.
Semico estimates that an made in 20-nm silicon that sells for $20 must ship 9.2 million units and achieve more than $180 million in revenue to breakeven.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.