IEEE has released the revised IEEE 1149.1-2013 “Standard for Test Access Port and Boundary-Scan Architecture”, commonly known in the industry as “JTAG,” for “Joint Test Action Group.”
This revision is intended to dramatically lower electronics industry costs by enabling test re-use across all phases of the integrated circuit lifecycle via vendor-independent, hierarchical test languages. The revision of IEEE 1149.1, the first for the standard since 2001, allows critical domain expertise for intellectual property (IP)—how to configure a serializer/deserializer (SERDES) for loopback testing, for example—to be transferred in a computer-readable format from the IP designer to IC designers and, in turn, to designers of printed circuit boards (PCBs) and to test engineers, gradually magnifying industry cost savings along the supply chain.
The cost savings for the electronics industry that IEEE 1149.1-2013 is intended to unlock are estimated to be in the billions of dollars. IEEE 1149.1-2013 specifies a new hierarchical Procedural Definition Language (PDL)—a standard test language based on Tcl, and hierarchical extensions to the original Boundary Scan Description Language (BSDL) to describe on-chip IP test data registers.
Eight new optional IC instructions provide a foundation for configuring I/Os for board test, mitigating false failures when re-testing the IC at the board level and correlating the results back to wafer level test through an Electronic Chip ID.
Now, the IP provider can document the IP test Interface and how to operate the IP in an English-like language—just once, for all ICs. Software tools then re-target this documentation at the IC and board level for tests. In revising IEEE 1149.1, the working group focused on two things: lowering industry costs through the new PDL language and enabling test re-use over the lifecycle of an integrated circuit.
IEEE 1149.1-2013 provides critical synergy with two other important industry standards. IEEE 1149.1-2013 supports segmented on-chip test data registers that cross power domains specified by IEEE 1801-2013 “Standard for Design and Verification of Low Power Integrated Circuits”. IEEE 1149.1-2013 enables descriptions and operation of IP accessible via IEEE 1500-2005 “Standard Testability Method for Embedded Core-based Integrated Circuits” structures. IEEE 1149.1-2013 domain segmentation adds new capability to the IEEE 1500 Wrapper Serial Ports.
The new features of iJTAG 1149.1-2013 enable yield ramp up by using a thing called ECID, Electronic Chip ID, which correlates system test back to the wafer position. They are using this for trackign the die from production to board/system test.
Along with that, I guess, there is a 'free ride' for also preventing counterfeiting through re-marking the part. The part will have a JTAG accessible ECID which tells you what speed grade, temperature grade or pass/fail status of the die. So no longer can one scrunge the trash bins of Intel to find parts which didnt pass and then sell them off as working parts. No longer can you erase the C temperature grade on the top of the chip and mark it as Industrial or AEC or MIL.