Researchers from IMEC (Leuven, Belgium) have created a nano-scale hafnium aluminum oxide dieleletric (HfAlO/Al2O3/HfAlO) stack as an inter-gate dielectric with a silicon/titanium-nitride hybrid floating gate in a planar NAND Flash structure.
IMEC said the three-layer structure that is high-k/low-k/high-k provides "excellent retention and endurance" of data. IMEC did not quantify this but endurance of 10^5 cycles is considered a practical lower limit for NAND memory. Retention of 10 years is the standard in most shipping non-volatile memories.
NAND flash memory has migrated to a planar structure at around 20-nm. The tightness of the memory cell pitch makes this necessary to avoid the wrapping the control gate round the floating gate. However, the planar cell therefore also demonstrates reduced coupling between control and floating gates making programming and reading harder.
The three-layer inter-gate dielectric has allowed an opening up of the program/erase window up to 18 volts. The dielectric is scalable in thickness making the material promising for further scaling of 2-D NAND flash memory below 20-nm, IMEC said.
Using a 25-nm thick stack (10-5-10) with an amorphous Al2O3 middle layer IMEC produced a large improvement over single Al2O3 dielectric layer. Retention tests showed little loss of charge at temperatures of 125 degrees C.
Click on image to enlarge.
Transmission electron microscopy pictures of the gate stack featuring a HfAlO/Al2O3/HfAlO inter-gate dielectric between the thin TiN from the hybrid floating gate and the TiN from the control gate. Source: IMEC.
The results were presented at the 2013 International Memory Workshop held in Monterey, Calif. from May 27 to 29.
I agree with NAND Rule. @20nm and below (I mean in BL and WL direction) It does not make any sense to speak about absolute reliability standard for the NAND (10 years, 3k or 50k or 100k cycles and at which T?). It depends on the use cases and the bib NAND users (A,SS) know it well...
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