SAN JOSE, Calif. – IBM and Oracle will disclose the first details of their next-generation server processors at the Hot Chips conference in August. The battle for big iron performance likely will generate the biggest news of more than two dozen papers at the annual event geared for processor designers.
IBM will discuss Power 8 and Oracle will talk about its M6 CPU and a related interconnect chip called Bixby at the event on the Stanford campus. Other talks at the event generally provide incremental details about chips already discussed elsewhere.
IBM’s previous Power 7 chip was hailed on its announcement as one of the most dense and scalable server chips of its time. “IBM has said next to nothing about Power 8, so this should be interesting,” said Nathan Brookwood, principal of market watcher Insight64 (Saratoga, Calif.).
Although Intel’s chips dominate the server market, it has little news in that sector right now. The x86 giant will talk about client versions of its 22nm Haswell processors coming to market this year. The heftier server versions of Haswell will mainly roll in 2014, making papers on them premature for this Hot Chips.
Likewise, FPGA leaders Altera and Xilinx only recently started talking about their next-generation chips. They were not able to field papers on them in time for the event.
In mobile, Intel is expected to provide some incremental details about its Atom-based Bay Trail SoC for tablets, formally announced at Computex, as well as its Clover Tail+ smartphone chip now shipping. AMD will counter with talks on its Kabini and Richland client x86 chips.
No new ARM-based SoCs will be disclosed at the event. “It’s more and more difficult to get people to talk [about app processors because] everyone is so worried about getting sued that they only talk under NDA to customers about what’s in them,” said Ralph Wittig, a member of the Hot Chips program committee.
Fittingly, Hot Chips will stray from its silicon focus for one keynote from an intellectual property lawyer.
Organizers were able to convince Qualcomm to give what is expected to be the first disclosure of the architecture of the Hexagon DSP core used in its baseband chips. Published benchmarks have rated the core highly among its competitors, Wittig said.
On the consumer front, Microsoft will talk about the previously disclosed silicon inside its new Xbox One. Separately, the program manager for Google’s Project Glass will talk about the server load generated by the glasses that pack an embedded computer, now the subject of a much watched beta test program.
it is becoming more interesting to watch end products like google glass...new gadgets, even though fundamental technologies are so important, end device is much more cool..Looking for cool devices conference.
There are only 3 ways to perform a computation faster*:
1) faster technology/clock rate,
2) do independent parts in parallel and combine,
3) use a better algorithm.
Assume that you have a computation that has parts that can be done in parallel (e.g, the "map" of a map-reduce), and sequential parts that can't be done in parallel (e.g., the final "reduce" step of a map-reduce). let's say 1/10 of the total time in spent in the serial part. Even if you have an infinite number of processors available and can drive the parallel parts to zero time, you can't get more than a 10X speedup. You also need a way to speed up the sequential part.
Assume you have a program that *might* be parallelizable, but nobody has yet gotten around to doing so, or that it would be hard enough to do that the programmer time to do the work would not justify the computing time saved over the number of runs made. Even with infinite CPUs available, such a program still runs 1X as fast as on a uniprocessor.
A Power8 or Sun M6 CPU is supposed to run sequential code faster than competing CPUs can run it. Sometimes that's important enough to spend whatever it costs to get even a few percentage points of improvement over the next-best thing.
* Per Professor David Kuck, of the University of Illinois and recently Intel, a pioneer in parallel processing. He probably still offers a bounty for a valid 4th method that isn't a combination of the other 3.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.