Some veteran networking experts are looking at the future beyond 100 Gbits/s and scratching their heads.
"We are starting to press some physical boundaries such as switching speeds of silicon and traces on printed circuit boards--and all of this is changing the cost dynamics," said Bob Grow, an Intel and IEEE executive who has worked on Ethernet standards and products since the Mbit generation.
In past generations, engineers solved the problems by packing more transistors in transmit and receiver circuits. They relied on the trend that the costs of those transistors became negligible within one or two generations of finer semiconductor process technologies.
Thus end users got ten times the bandwidth for essentially the same price every two years or so. Engineers may not be able to bank on that trend for the terabit generation.
"In the hunger for higher bandwidth it becomes increasingly difficult meet the increasingly lower cost per bit requirements," Grow said. "I don't believe we can continue to push these limits," he said.
Indeed, engineers said the draft specifications for 25 Gbit/second serial-deserializers, called serdes unveiled last week at a meeting of the Optical Internetworking Forum are essentially based on pushing both silicon and board materials to the max. Serdes are the basic I/O building blocks out of which virtually all today's high-speed chips are built.
The 25G serial standard is meant to relieve pressure on first-generation 100 Gbit Ethernet products being built today using ten lanes of 10 Gbit/s serial links, today's fastest interfaces. "It's ugly" implementing in products the twenty 10 Gbit links needed to deliver two-way signaling in such products, said one engineer.
Ten 10 Gbit links packed together in a chip or board trace is "a breeding ground for crosstalk" said Ransom Stephens, a signal integrity consultant, speaking on a panel at DesignCon.
The 25G serdes could reduce to just four the number of parallel high-speed channels needed for 100G Ethernet chips. But achieving such serial speeds presents its own set of thorny signal integrity problems. Assuming engineers solve those issues, the 25G lanes will ultimately be used to build a new set of interfaces that will present even greater challenges.
D'Ambrosia and others are already floating the idea of packing 16 of the emerging 25G links together. The technique could deliver 400 Gbit Ethernet products that could take some of the edge off the cries for terabit Ethernet, they suggested.
"I argue 400 Gbit is the next logical Ethernet speed," said D'Ambrosia at the OIF meeting.